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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-28 15:35:22 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-09-28 15:58:21 +0800 |
| commit | 4b6b0bf24a043035d7ada0c966e01df6327dc529 (patch) | |
| tree | 9f8ca7140d286e274158105f77b5939b7424f18b /src/mesa/drivers/dri/i965/gen6_scissor_state.c | |
| parent | 3f3059fcc0cfb797830eb5e0755b5b4ec3fd218b (diff) | |
| download | external_mesa3d-4b6b0bf24a043035d7ada0c966e01df6327dc529.zip external_mesa3d-4b6b0bf24a043035d7ada0c966e01df6327dc529.tar.gz external_mesa3d-4b6b0bf24a043035d7ada0c966e01df6327dc529.tar.bz2 | |
i965: fix scissor state on sandybridge
Fix incorrect scissor rect struct and missed scissor state pointer
setting for sandybridge.
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen6_scissor_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_scissor_state.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_scissor_state.c b/src/mesa/drivers/dri/i965/gen6_scissor_state.c index 34a9dc2..3d483c7 100644 --- a/src/mesa/drivers/dri/i965/gen6_scissor_state.c +++ b/src/mesa/drivers/dri/i965/gen6_scissor_state.c @@ -35,7 +35,7 @@ prepare_scissor_state(struct brw_context *brw) { GLcontext *ctx = &brw->intel.ctx; const GLboolean render_to_fbo = (ctx->DrawBuffer->Name != 0); - struct gen6_scissor_state scissor; + struct gen6_scissor_rect scissor; /* _NEW_SCISSOR | _NEW_BUFFERS | _NEW_VIEWPORT */ @@ -84,7 +84,6 @@ static void upload_scissor_state_pointers(struct brw_context *brw) OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); ADVANCE_BATCH(); - intel_batchbuffer_emit_mi_flush(intel->batch); } |