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| author | Paul Berry <stereotype441@gmail.com> | 2013-08-31 20:23:49 -0700 |
|---|---|---|
| committer | Paul Berry <stereotype441@gmail.com> | 2013-09-05 09:52:47 -0700 |
| commit | 588ec545acc930470c605005292c8ef10adf4919 (patch) | |
| tree | eab7ffc66da90f8106ec7fe4c98e02c4d36d496d /src/mesa/drivers/dri/i965/gen6_urb.c | |
| parent | ae79e3332eca5c8024c894c7c7689bfbf3311038 (diff) | |
| download | external_mesa3d-588ec545acc930470c605005292c8ef10adf4919.zip external_mesa3d-588ec545acc930470c605005292c8ef10adf4919.tar.gz external_mesa3d-588ec545acc930470c605005292c8ef10adf4919.tar.bz2 | |
i965/gen7.5: Fix lower bound on number of VS URB entries.
Haswell GT2 and GT3 require the number of vertex shader URB entries to
be at least 64, not 32.
At the moment, we always meet this requirement automatically, because
in the absence of a geometry shader, we assign all available URB space
to the vertex shader. But when we turn on support for geometry
shaders, this lower limit will become important.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen6_urb.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_urb.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c index e16d30a..bb4cfa8 100644 --- a/src/mesa/drivers/dri/i965/gen6_urb.c +++ b/src/mesa/drivers/dri/i965/gen6_urb.c @@ -83,7 +83,7 @@ gen6_upload_urb( struct brw_context *brw ) brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4); brw->urb.nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, 4); - assert(brw->urb.nr_vs_entries >= 24); + assert(brw->urb.nr_vs_entries >= brw->urb.min_vs_entries); assert(brw->urb.nr_vs_entries % 4 == 0); assert(brw->urb.nr_gs_entries % 4 == 0); assert(vs_size < 5); |