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| author | Kenneth Graunke <kenneth@whitecape.org> | 2011-11-01 10:54:08 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2011-11-10 22:51:19 -0800 |
| commit | 6ba9090ea05e817bd38c1fcc63c53168b16593c7 (patch) | |
| tree | fefb9ecff7cd5ef9227228fae00bb664fc86acdc /src/mesa/drivers/dri/i965/gen6_vs_state.c | |
| parent | 0983c6869bead0c31c62e5b1dda7f70898d43971 (diff) | |
| download | external_mesa3d-6ba9090ea05e817bd38c1fcc63c53168b16593c7.zip external_mesa3d-6ba9090ea05e817bd38c1fcc63c53168b16593c7.tar.gz external_mesa3d-6ba9090ea05e817bd38c1fcc63c53168b16593c7.tar.bz2 | |
i965: Use 0 for the number of binding table entries in 3DSTATE_(VS|WM).
These fields control how many entries the hardware prefetches into the
state cache, so they only impact performance, not correctness. However,
it's not clear how to use this in a way that's beneficial.
According to the documentation, kernels "using a large number" of
entries may wish to program this to zero to avoid thrashing the cache;
it's unclear how many is too many. Also, Ironlake's WM was missing this
feature entirely---the count had to be zero.
The dirty bit tracking to handle this complicates the surface state
and binding table setup; removing it should simplify things and make
future refactoring easier. So just set 0 for the number of entries
rather than trying to compute and track it.
Appears to have no impact on Nexuiz and OpenArena on Sandybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen6_vs_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_vs_state.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c index e22fd39..7ea7e21 100644 --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c @@ -167,9 +167,7 @@ upload_vs_state(struct brw_context *brw) BEGIN_BATCH(6); OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2)); OUT_BATCH(brw->vs.prog_offset); - OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) | - floating_point_mode | - (brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); + OUT_BATCH(floating_point_mode | (0 << GEN6_VS_SAMPLER_COUNT_SHIFT)); if (brw->vs.prog_data->total_scratch) { OUT_RELOC(brw->vs.scratch_bo, @@ -220,8 +218,7 @@ upload_vs_state(struct brw_context *brw) const struct brw_tracked_state gen6_vs_state = { .dirty = { .mesa = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS, - .brw = (BRW_NEW_NR_VS_SURFACES | - BRW_NEW_URB_FENCE | + .brw = (BRW_NEW_URB_FENCE | BRW_NEW_CONTEXT | BRW_NEW_VERTEX_PROGRAM | BRW_NEW_BATCH), |