i965: Store floating point mode choice in brw_stage_prog_data.

We use IEEE mode for GLSL programs, but need to use ALT mode for ARB
programs so that 0^0 == 1.  The choice is based entirely on the shader
source language.

Previously, our code to determine which mode we wanted was duplicated
in 8 different places (VS and FS for Gen4-5, Gen6, Gen7, and Gen8).
The ctx->_Shader->CurrentProgram[stage] == NULL check was confusing
as well - we use CurrentProgram (non-derived state), but _Shader
(derived state).  It also relies on knowing that ARB programs don't
use gl_shader_program structures today.  The compiler already makes
this assumption in a few places, but I'd rather keep that assumption
out of the state upload code.

With this patch, we select the mode at compile time, and store that
choice in prog_data.  The state upload code simply uses that decision.

This eliminates a BRW_NEW_*_PROGRAM dependency in the state upload code.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

1 files changed, 1 insertions, 6 deletions

diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 4ac91af..e57b7f6 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -115,12 +115,7 @@ upload_wm_state(struct brw_context *brw)
    dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
    dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
 
-   /* Use ALT floating point mode for ARB fragment programs, because they
-    * require 0^0 == 1.  Even though _CurrentFragmentProgram is used for
-    * rendering, CurrentProgram[MESA_SHADER_FRAGMENT] is used for this check
-    * to differentiate between the GLSL and non-GLSL cases.
-    */
-   if (ctx->_Shader->CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
+   if (prog_data->base.use_alt_mode)
       dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
 
    dw2 |= (ALIGN(brw->wm.base.sampler_count, 4) / 4) <<