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author | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-05-10 11:17:27 -0700 |
---|---|---|
committer | Jason Ekstrand <jason.ekstrand@intel.com> | 2016-05-14 13:34:10 -0700 |
commit | b0f8768905c84b3aa69a44030d998d1076d77728 (patch) | |
tree | 9294e5cdf785074e86d523da8bdced6089438353 /src/mesa/drivers/dri/i965/gen6_wm_state.c | |
parent | 712a980adde0b14eee8b4accd02af9b9740091a2 (diff) | |
download | external_mesa3d-b0f8768905c84b3aa69a44030d998d1076d77728.zip external_mesa3d-b0f8768905c84b3aa69a44030d998d1076d77728.tar.gz external_mesa3d-b0f8768905c84b3aa69a44030d998d1076d77728.tar.bz2 |
i965/state: Clean up WM/PS state to pull more things out of prog_data
Now that we have a persample_shading bit in prog_data we can reduce the
amount the state setup code needs to be looking at the GL state. In
particular, it no longer pulls anything directly out of the
gl_fragment_program and no longer depends on NEW_FRAGMENT_PROGRAM.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen6_wm_state.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/gen6_wm_state.c | 28 |
1 files changed, 8 insertions, 20 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c index dd33926..4a5aa12 100644 --- a/src/mesa/drivers/dri/i965/gen6_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c @@ -69,10 +69,9 @@ const struct brw_tracked_state gen6_wm_push_constants = { void gen6_upload_wm_state(struct brw_context *brw, - const struct brw_fragment_program *fp, const struct brw_wm_prog_data *prog_data, const struct brw_stage_state *stage_state, - bool multisampled_fbo, int min_inv_per_frag, + bool multisampled_fbo, bool dual_source_blend_enable, bool kill_enable, bool color_buffer_write_enable, bool msaa_enabled, bool line_stipple_enable, bool polygon_stipple_enable, @@ -163,10 +162,11 @@ gen6_upload_wm_state(struct brw_context *brw, if (polygon_stipple_enable) dw5 |= GEN6_WM_POLYGON_STIPPLE_ENABLE; - /* BRW_NEW_FRAGMENT_PROGRAM */ - if (fp->program.Base.InputsRead & VARYING_BIT_POS) - dw5 |= GEN6_WM_USES_SOURCE_DEPTH | GEN6_WM_USES_SOURCE_W; - if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) + if (prog_data->uses_src_depth) + dw5 |= GEN6_WM_USES_SOURCE_DEPTH; + if (prog_data->uses_src_w) + dw5 |= GEN6_WM_USES_SOURCE_W; + if (prog_data->computed_depth_mode != BRW_PSCDEPTH_OFF) dw5 |= GEN6_WM_COMPUTED_DEPTH; dw6 |= prog_data->barycentric_interp_modes << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; @@ -277,23 +277,12 @@ static void upload_wm_state(struct brw_context *brw) { struct gl_context *ctx = &brw->ctx; - /* BRW_NEW_FRAGMENT_PROGRAM */ - const struct brw_fragment_program *fp = - brw_fragment_program_const(brw->fragment_program); /* BRW_NEW_FS_PROG_DATA */ const struct brw_wm_prog_data *prog_data = brw->wm.prog_data; /* _NEW_BUFFERS */ const bool multisampled_fbo = _mesa_geometric_samples(ctx->DrawBuffer) > 1; - /* In case of non 1x per sample shading, only one of SIMD8 and SIMD16 - * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader - * is successfully compiled. In majority of the cases that bring us - * better performance than 'SIMD8 only' dispatch. - */ - const int min_inv_per_frag = _mesa_get_min_invocations_per_fragment( - ctx, brw->fragment_program, false); - /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR */ const bool dual_src_blend_enable = prog_data->dual_src_blend && (ctx->Color.BlendEnabled & 1) && @@ -310,8 +299,8 @@ upload_wm_state(struct brw_context *brw) /* _NEW_LINE | _NEW_POLYGON | _NEW_BUFFERS | _NEW_COLOR | * _NEW_MULTISAMPLE */ - gen6_upload_wm_state(brw, fp, prog_data, &brw->wm.base, - multisampled_fbo, min_inv_per_frag, + gen6_upload_wm_state(brw, prog_data, &brw->wm.base, + multisampled_fbo, dual_src_blend_enable, kill_enable, brw_color_buffer_write_enabled(brw), ctx->Multisample.Enabled, @@ -329,7 +318,6 @@ const struct brw_tracked_state gen6_wm_state = { _NEW_PROGRAM_CONSTANTS, .brw = BRW_NEW_BATCH | BRW_NEW_BLORP | - BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_FS_PROG_DATA | BRW_NEW_PUSH_CONSTANT_ALLOCATION, }, |