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| author | Paul Berry <stereotype441@gmail.com> | 2013-05-01 08:04:12 -0700 |
|---|---|---|
| committer | Paul Berry <stereotype441@gmail.com> | 2013-06-12 11:10:06 -0700 |
| commit | 5e5d4e021f7dde12fb0f4dfaf40fbbd4d119f4ab (patch) | |
| tree | e57a14e96f071bdefc593d1402b0c18ad4c25807 /src/mesa/drivers/dri/i965/gen7_blorp.cpp | |
| parent | dd3f950115218c69c9118436a5110a1ee6a2dda5 (diff) | |
| download | external_mesa3d-5e5d4e021f7dde12fb0f4dfaf40fbbd4d119f4ab.zip external_mesa3d-5e5d4e021f7dde12fb0f4dfaf40fbbd4d119f4ab.tar.gz external_mesa3d-5e5d4e021f7dde12fb0f4dfaf40fbbd4d119f4ab.tar.bz2 | |
i965/gen7+: Implement fast color clear operation in BLORP.
Since we defer allocation of the MCS miptree until the time of the
fast clear operation, this patch also implements creation of the MCS
miptree.
In addition, this patch adds the field
intel_mipmap_tree::fast_clear_color_value, which holds the most recent
fast color clear value, if any. We use it to set the SURFACE_STATE's
clear color for render targets.
v2: Flag BRW_NEW_SURFACES when allocating the MCS miptree. Generate a
perf_debug message if clearing to a color that isn't compatible with
fast color clear. Fix "control reaches end of non-void function"
build warning.
Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_blorp.cpp')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_blorp.cpp | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index 208c66a..1b2d309 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -199,11 +199,13 @@ gen7_blorp_emit_surface_state(struct brw_context *brw, is_render_target); } + surf[7] = surface->mt->fast_clear_color_value; + if (intel->is_haswell) { - surf[7] = SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | - SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | - SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | - SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); + surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | + SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | + SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | + SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A)); } /* Emit relocation to surface contents */ @@ -584,6 +586,14 @@ gen7_blorp_emit_ps_config(struct brw_context *brw, dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0; } + switch (params->fast_clear_op) { + case GEN7_FAST_CLEAR_OP_FAST_CLEAR: + dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE; + break; + default: + break; + } + BEGIN_BATCH(8); OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2)); OUT_BATCH(params->use_wm_prog ? prog_offset : 0); |