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| author | Chad Versace <chad.versace@linux.intel.com> | 2013-07-18 10:04:17 -0700 |
|---|---|---|
| committer | Chad Versace <chad.versace@linux.intel.com> | 2013-07-18 16:18:22 -0700 |
| commit | 2273b652bb884a6188af7f8d063d0d0fc5497054 (patch) | |
| tree | d32ea20bfe8cb36dce82f3772ddb7b346efe982f /src/mesa/drivers/dri/i965/gen7_vs_state.c | |
| parent | 2f346395f5109c0fc4db86de3d2754001ddf0bb9 (diff) | |
| download | external_mesa3d-2273b652bb884a6188af7f8d063d0d0fc5497054.zip external_mesa3d-2273b652bb884a6188af7f8d063d0d0fc5497054.tar.gz external_mesa3d-2273b652bb884a6188af7f8d063d0d0fc5497054.tar.bz2 | |
i965/hsw: Change L3 MOCS of 3DSTATE_CONSTANT_VS/PS
Change from "not cacheable" to "cacheable" in L3.
Do so for the draw upload path and blorp.
In blorp, change only the PS packet, because the VS packet is disabled.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_vs_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_vs_state.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c index 7369a9c..0340da4 100644 --- a/src/mesa/drivers/dri/i965/gen7_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c @@ -63,6 +63,8 @@ upload_vs_state(struct brw_context *brw) OUT_BATCH(0); ADVANCE_BATCH(); } else { + uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + BEGIN_BATCH(7); OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2)); OUT_BATCH(brw->vs.push_const_size); @@ -70,7 +72,7 @@ upload_vs_state(struct brw_context *brw) /* Pointer to the VS constant buffer. Covered by the set of * state flags from gen6_prepare_wm_contants */ - OUT_BATCH(brw->vs.push_const_offset); + OUT_BATCH(brw->vs.push_const_offset | mocs); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); |