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| author | Kevin Rogovin <kevin.rogovin@intel.com> | 2015-06-17 13:29:57 +0300 |
|---|---|---|
| committer | Martin Peres <martin.peres@linux.intel.com> | 2015-06-17 14:39:03 +0300 |
| commit | 9ded6369754910f7f58f896c1627ba0bbfb0f864 (patch) | |
| tree | 609e3d360acade13a1dc4f4bdeefdb2bbd19b904 /src/mesa/drivers/dri/i965/gen7_wm_state.c | |
| parent | bbb700967e9991a03ed6e8073c9bdc2ca0d1381d (diff) | |
| download | external_mesa3d-9ded6369754910f7f58f896c1627ba0bbfb0f864.zip external_mesa3d-9ded6369754910f7f58f896c1627ba0bbfb0f864.tar.gz external_mesa3d-9ded6369754910f7f58f896c1627ba0bbfb0f864.tar.bz2 | |
i965: execution of frag-shader when it has atomic buffer
Ensure that the GPU spawns the fragment shader thread for those
fragment shaders with atomic buffer access.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_state.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 1c47076..ea11ae8 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -77,6 +77,10 @@ upload_wm_state(struct brw_context *brw) dw1 |= GEN7_WM_KILL_ENABLE; } + if (_mesa_active_fragment_shader_has_atomic_ops(&brw->ctx)) { + dw1 |= GEN7_WM_DISPATCH_ENABLE; + } + /* _NEW_BUFFERS | _NEW_COLOR */ if (brw_color_buffer_write_enabled(brw) || writes_depth || dw1 & GEN7_WM_KILL_ENABLE) { |