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| author | Kenneth Graunke <kenneth@whitecape.org> | 2013-09-01 17:31:54 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-09-13 14:26:52 -0700 |
| commit | 4b3c0a797f89830fd5ba0943b061abf4fc38337e (patch) | |
| tree | 15b3d96c8025abe674611b223712f959706b6866 /src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | |
| parent | e6e5f888480c2ca87e6bcca8ee0cc5d3925ddd4a (diff) | |
| download | external_mesa3d-4b3c0a797f89830fd5ba0943b061abf4fc38337e.zip external_mesa3d-4b3c0a797f89830fd5ba0943b061abf4fc38337e.tar.gz external_mesa3d-4b3c0a797f89830fd5ba0943b061abf4fc38337e.tar.bz2 | |
i965: Use brw_stage_state for WM data as well.
This gets the VS, GS, and PS all using the same data structure.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_surface_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index c2c6605..37e3174 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -465,7 +465,7 @@ gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit) const struct gl_framebuffer *fb = ctx->DrawBuffer; uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, - &brw->wm.surf_offset[SURF_INDEX_DRAW(unit)]); + &brw->wm.base.surf_offset[SURF_INDEX_DRAW(unit)]); memset(surf, 0, 8 * 4); /* From the Ivybridge PRM, Volume 4, Part 1, page 65, @@ -510,7 +510,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, uint32_t surf_index = SURF_INDEX_DRAW(unit); uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, - &brw->wm.surf_offset[surf_index]); + &brw->wm.base.surf_offset[surf_index]); memset(surf, 0, 8 * 4); intel_miptree_used_for_rendering(irb->mt); @@ -579,7 +579,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT; if (irb->mt->mcs_mt) { - gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[surf_index], + gen7_set_surface_mcs_info(brw, surf, brw->wm.base.surf_offset[surf_index], irb->mt->mcs_mt, true /* is RT */); } @@ -593,7 +593,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, } drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.surf_offset[surf_index] + 4, + brw->wm.base.surf_offset[surf_index] + 4, region->bo, surf[1] - region->bo->offset, I915_GEM_DOMAIN_RENDER, |