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| author | Paul Berry <stereotype441@gmail.com> | 2013-05-07 14:04:29 -0700 |
|---|---|---|
| committer | Paul Berry <stereotype441@gmail.com> | 2013-06-12 10:45:42 -0700 |
| commit | 7e5cb4bc4c8dfc96019b815e2c9a62af12e1f958 (patch) | |
| tree | e19056fa80ed2927368939232d3d1d5f45b02e4c /src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | |
| parent | 8f5147c199748ae129c527322823c2b40fb36941 (diff) | |
| download | external_mesa3d-7e5cb4bc4c8dfc96019b815e2c9a62af12e1f958.zip external_mesa3d-7e5cb4bc4c8dfc96019b815e2c9a62af12e1f958.tar.gz external_mesa3d-7e5cb4bc4c8dfc96019b815e2c9a62af12e1f958.tar.bz2 | |
i965/gen7+: Create an enum for keeping track of fast color clear state.
This patch includes code to update the fast color clear state
appropriately when rendering occurs. The state will also need to be
updated when a fast clear or a resolve operation is performed; those
state updates will be added when the fast clear and resolve operations
are added.
v2: Create a new function, intel_miptree_used_for_rendering() to
handle updating the fast color clear state when rendering occurs.
Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_surface_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 22ceaa5..6a7c8de 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -545,6 +545,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, 8 * 4, 32, &brw->wm.surf_offset[unit]); memset(surf, 0, 8 * 4); + intel_miptree_used_for_rendering(irb->mt); + /* Render targets can't use IMS layout */ assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS); |