i965: Replace structs with bit-shifting for Gen7 SURFACE_STATE entries.

Every generation except Gen7 creates SURFACE_STATE entries via a
uint32_t array.  Only Gen7 uses the older bitfield structure, which we
moved away from because it was less efficient.  Convert it for
consistency.

This reduces the compiled size of gen7_wm_surface_state.o by 2.86% in a
release build.

v2: Fix accidental use of BRW_SURFACE_WIDTH/HEIGHT in brw_state_dump.c;
    switch back to gen7_set_surface_mcs_info setting surf[6] directly
    (both per Eric's review comments).

Acked-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

1 files changed, 166 insertions, 203 deletions

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 1e5af95..13e8ba8 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -61,47 +61,44 @@ swizzle_to_scs(GLenum swizzle)
    return HSW_SCS_ZERO;
 }
 
-void
-gen7_set_surface_tiling(struct gen7_surface_state *surf, uint32_t tiling)
+uint32_t
+gen7_surface_tiling_mode(uint32_t tiling)
 {
    switch (tiling) {
-   case I915_TILING_NONE:
-      surf->ss0.tiled_surface = 0;
-      surf->ss0.tile_walk = 0;
-      break;
    case I915_TILING_X:
-      surf->ss0.tiled_surface = 1;
-      surf->ss0.tile_walk = BRW_TILEWALK_XMAJOR;
-      break;
+      return GEN7_SURFACE_TILING_X;
    case I915_TILING_Y:
-      surf->ss0.tiled_surface = 1;
-      surf->ss0.tile_walk = BRW_TILEWALK_YMAJOR;
-      break;
+      return GEN7_SURFACE_TILING_Y;
+   default:
+      return GEN7_SURFACE_TILING_NONE;
    }
 }
 
 
-void
-gen7_set_surface_msaa(struct gen7_surface_state *surf, unsigned num_samples,
-                      enum intel_msaa_layout layout)
+uint32_t
+gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout layout)
 {
+   uint32_t ss4 = 0;
+
    if (num_samples > 4)
-      surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_8;
+      ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_8;
    else if (num_samples > 1)
-      surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_4;
+      ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_4;
+   else
+      ss4 |= GEN7_SURFACE_MULTISAMPLECOUNT_1;
+
+   if (layout == INTEL_MSAA_LAYOUT_IMS)
+      ss4 |= GEN7_SURFACE_MSFMT_DEPTH_STENCIL;
    else
-      surf->ss4.num_multisamples = GEN7_SURFACE_MULTISAMPLECOUNT_1;
+      ss4 |= GEN7_SURFACE_MSFMT_MSS;
 
-   surf->ss4.multisampled_surface_storage_format =
-      layout == INTEL_MSAA_LAYOUT_IMS ?
-      GEN7_SURFACE_MSFMT_DEPTH_STENCIL :
-      GEN7_SURFACE_MSFMT_MSS;
+   return ss4;
 }
 
 
 void
 gen7_set_surface_mcs_info(struct brw_context *brw,
-                          struct gen7_surface_state *surf,
+                          uint32_t *surf,
                           uint32_t surf_offset,
                           const struct intel_mipmap_tree *mcs_mt,
                           bool is_render_target)
@@ -125,14 +122,15 @@ gen7_set_surface_mcs_info(struct brw_context *brw,
     * the necessary address translation.
     */
    assert ((mcs_mt->region->bo->offset & 0xfff) == 0);
-   surf->ss6.mcs_enabled.mcs_enable = 1;
-   surf->ss6.mcs_enabled.mcs_surface_pitch = pitch_tiles - 1;
-   surf->ss6.mcs_enabled.mcs_base_address = mcs_mt->region->bo->offset >> 12;
+
+   surf[6] = GEN7_SURFACE_MCS_ENABLE |
+             SET_FIELD(pitch_tiles - 1, GEN7_SURFACE_MCS_PITCH) |
+             mcs_mt->region->bo->offset;
+
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-                           surf_offset +
-                           offsetof(struct gen7_surface_state, ss6),
+                           surf_offset + 6 * 4,
                            mcs_mt->region->bo,
-                           surf->ss6.raw_data & 0xfff,
+                           surf[6] & 0xfff,
                            is_render_target ? I915_GEM_DOMAIN_RENDER
                            : I915_GEM_DOMAIN_SAMPLER,
                            is_render_target ? I915_GEM_DOMAIN_RENDER : 0);
@@ -140,11 +138,15 @@ gen7_set_surface_mcs_info(struct brw_context *brw,
 
 
 void
-gen7_check_surface_setup(struct gen7_surface_state *surf,
-                         bool is_render_target)
+gen7_check_surface_setup(uint32_t *surf, bool is_render_target)
 {
-   bool is_multisampled =
-      surf->ss4.num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
+   unsigned num_multisamples = surf[4] & INTEL_MASK(5, 3);
+   unsigned multisampled_surface_storage_format = surf[4] & (1 << 6);
+   unsigned surface_array_spacing = surf[0] & (1 << 10);
+   bool is_multisampled = num_multisamples != GEN7_SURFACE_MULTISAMPLECOUNT_1;
+
+   (void) surface_array_spacing;
+
    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
     * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Surface Array
     * Spacing:
@@ -153,9 +155,9 @@ gen7_check_surface_setup(struct gen7_surface_state *surf,
     *   Multisamples is not MULTISAMPLECOUNT_1, this field must be set to
     *   ARYSPC_LOD0.
     */
-   if (surf->ss4.multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
+   if (multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS
        && is_multisampled)
-      assert(surf->ss0.surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
+      assert(surface_array_spacing == GEN7_SURFACE_ARYSPC_LOD0);
 
    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
     * SURFACE_STATE > SURFACE_STATE for most messages [DevIVB]: Multisampled
@@ -169,8 +171,7 @@ gen7_check_surface_setup(struct gen7_surface_state *surf,
     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
     */
    if (is_render_target && is_multisampled) {
-      assert(surf->ss4.multisampled_surface_storage_format ==
-             GEN7_SURFACE_MSFMT_MSS);
+      assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
    }
 
    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
@@ -181,10 +182,9 @@ gen7_check_surface_setup(struct gen7_surface_state *surf,
     *   is >= 8192 (meaning the actual surface width is >= 8193 pixels), this
     *   field must be set to MSFMT_MSS.
     */
-   if (surf->ss4.num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
-       surf->ss2.width >= 8192) {
-      assert(surf->ss4.multisampled_surface_storage_format ==
-             GEN7_SURFACE_MSFMT_MSS);
+   uint32_t width = GET_FIELD(surf[2], GEN7_SURFACE_WIDTH) + 1;
+   if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 && width >= 8193) {
+      assert(multisampled_surface_storage_format == GEN7_SURFACE_MSFMT_MSS);
    }
 
    /* From the Graphics BSpec: vol5c Shared Functions [SNB+] > State >
@@ -203,25 +203,25 @@ gen7_check_surface_setup(struct gen7_surface_state *surf,
     *
     *   This field is ignored if Number of Multisamples is MULTISAMPLECOUNT_1.
     */
-   uint32_t depth = surf->ss3.depth + 1;
-   uint32_t height = surf->ss2.height + 1;
-   if (surf->ss4.num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
+   uint32_t depth = GET_FIELD(surf[3], BRW_SURFACE_DEPTH) + 1;
+   uint32_t height = GET_FIELD(surf[2], GEN7_SURFACE_HEIGHT) + 1;
+   if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_8 &&
        depth * height > 4194304) {
-      assert(surf->ss4.multisampled_surface_storage_format ==
+      assert(multisampled_surface_storage_format ==
              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
    }
-   if (surf->ss4.num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
+   if (num_multisamples == GEN7_SURFACE_MULTISAMPLECOUNT_4 &&
        depth * height > 8388608) {
-      assert(surf->ss4.multisampled_surface_storage_format ==
+      assert(multisampled_surface_storage_format ==
              GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
    }
    if (is_multisampled) {
-      switch (surf->ss0.surface_format) {
+      switch (GET_FIELD(surf[0], BRW_SURFACE_FORMAT)) {
       case BRW_SURFACEFORMAT_I24X8_UNORM:
       case BRW_SURFACEFORMAT_L24X8_UNORM:
       case BRW_SURFACEFORMAT_A24X8_UNORM:
       case BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS:
-         assert(surf->ss4.multisampled_surface_storage_format ==
+         assert(multisampled_surface_storage_format ==
                 GEN7_SURFACE_MSFMT_DEPTH_STENCIL);
       }
    }
@@ -235,56 +235,47 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx,
                                    unsigned surf_index)
 {
    struct brw_context *brw = brw_context(ctx);
+   struct intel_context *intel = &brw->intel;
    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
-   struct gen7_surface_state *surf;
    struct intel_buffer_object *intel_obj =
       intel_buffer_object(tObj->BufferObject);
    drm_intel_bo *bo = intel_obj ? intel_obj->buffer : NULL;
    gl_format format = tObj->_BufferObjectFormat;
-   int texel_size = _mesa_get_format_bytes(format);
-
-   surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-			  sizeof(*surf), 32, &binding_table[surf_index]);
-   memset(surf, 0, sizeof(*surf));
 
-   surf->ss0.surface_type = BRW_SURFACE_BUFFER;
-   surf->ss0.surface_format = brw_format_for_mesa_format(format);
+   uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+                                    8 * 4, 32, &binding_table[surf_index]);
+   memset(surf, 0, 8 * 4);
 
-   surf->ss0.render_cache_read_write = 1;
-
-   if (surf->ss0.surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
+   uint32_t surface_format = brw_format_for_mesa_format(format);
+   if (surface_format == 0 && format != MESA_FORMAT_RGBA_FLOAT32) {
       _mesa_problem(NULL, "bad format %s for texture buffer\n",
-		    _mesa_get_format_name(format));
+                    _mesa_get_format_name(format));
    }
 
+   surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
+             surface_format << BRW_SURFACE_FORMAT_SHIFT |
+             BRW_SURFACE_RC_READ_WRITE;
+
    if (bo) {
-      surf->ss1.base_addr = bo->offset; /* reloc */
+      surf[1] = bo->offset; /* reloc */
 
       /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
        * bspec ("Data Cache") says that the data cache does not exist as
        * a separate cache and is just the sampler cache.
        */
-      drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-			      (binding_table[surf_index] +
-			       offsetof(struct gen7_surface_state, ss1)),
+      drm_intel_bo_emit_reloc(intel->batch.bo,
+			      binding_table[surf_index] + 4,
 			      bo, 0,
 			      I915_GEM_DOMAIN_SAMPLER, 0);
 
+      int texel_size = _mesa_get_format_bytes(format);
       int w = intel_obj->Base.Size / texel_size;
-      surf->ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
-      surf->ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
-      surf->ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
-      surf->ss3.pitch = texel_size - 1;
-} else {
-      surf->ss1.base_addr = 0;
-      surf->ss2.width = 0;
-      surf->ss2.height = 0;
-      surf->ss3.depth = 0;
-      surf->ss3.pitch = 0;
+      surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) | /* bits 6:0 of size */
+                SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT); /* 19:7 */
+      surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) | /* bits 26:20 */
+                (texel_size - 1);
    }
 
-   gen7_set_surface_tiling(surf, I915_TILING_NONE);
-
    gen7_check_surface_setup(surf, false /* is_render_target */);
 }
 
@@ -295,12 +286,12 @@ gen7_update_texture_surface(struct gl_context *ctx,
                             unsigned surf_index)
 {
    struct brw_context *brw = brw_context(ctx);
+   struct intel_context *intel = &brw->intel;
    struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
    struct intel_texture_object *intelObj = intel_texture_object(tObj);
    struct intel_mipmap_tree *mt = intelObj->mt;
    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
-   struct gen7_surface_state *surf;
    int width, height, depth;
 
    if (tObj->Target == GL_TEXTURE_BUFFER) {
@@ -314,62 +305,38 @@ gen7_update_texture_surface(struct gl_context *ctx,
 
    intel_miptree_get_dimensions_for_image(firstImage, &width, &height, &depth);
 
-   surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-			  sizeof(*surf), 32, &binding_table[surf_index]);
-   memset(surf, 0, sizeof(*surf));
-
-   if (mt->align_h == 4)
-      surf->ss0.vertical_alignment = 1;
-   if (mt->align_w == 8)
-      surf->ss0.horizontal_alignment = 1;
-
-   surf->ss0.surface_type = translate_tex_target(tObj->Target);
-   surf->ss0.surface_format = translate_tex_format(mt->format,
-                                                   firstImage->InternalFormat,
-                                                   tObj->DepthMode,
-                                                   sampler->sRGBDecode);
-   if (tObj->Target == GL_TEXTURE_CUBE_MAP ||
-       tObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
-      surf->ss0.cube_pos_x = 1;
-      surf->ss0.cube_pos_y = 1;
-      surf->ss0.cube_pos_z = 1;
-      surf->ss0.cube_neg_x = 1;
-      surf->ss0.cube_neg_y = 1;
-      surf->ss0.cube_neg_z = 1;
-   }
-
-   surf->ss0.is_array = depth > 1 && tObj->Target != GL_TEXTURE_3D;
+   uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+                                    8 * 4, 32, &binding_table[surf_index]);
+   memset(surf, 0, 8 * 4);
 
-   gen7_set_surface_tiling(surf, intelObj->mt->region->tiling);
+   uint32_t tex_format = translate_tex_format(mt->format,
+                                              firstImage->InternalFormat,
+                                              tObj->DepthMode,
+                                              sampler->sRGBDecode);
 
-   /* ss0 remaining fields:
-    * - vert_line_stride (exists on gen6 but we ignore it)
-    * - vert_line_stride_ofs (exists on gen6 but we ignore it)
-    * - surface_array_spacing
-    * - render_cache_read_write (exists on gen6 but ignored here)
-    */
-
-   surf->ss1.base_addr =
-      intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
+   surf[0] = translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
+             tex_format << BRW_SURFACE_FORMAT_SHIFT |
+             gen7_surface_tiling_mode(mt->region->tiling) |
+             BRW_SURFACE_CUBEFACE_ENABLES;
 
-   surf->ss2.width = width - 1;
-   surf->ss2.height = height - 1;
+   if (mt->align_h == 4)
+      surf[0] |= GEN7_SURFACE_VALIGN_4;
+   if (mt->align_w == 8)
+      surf[0] |= GEN7_SURFACE_HALIGN_8;
 
-   surf->ss3.pitch = (intelObj->mt->region->pitch * intelObj->mt->cpp) - 1;
-   surf->ss3.depth = depth - 1;
+   if (depth > 1 && tObj->Target != GL_TEXTURE_3D)
+      surf[0] |= GEN7_SURFACE_IS_ARRAY;
 
-   /* ss4: ignored? */
+   surf[1] = mt->region->bo->offset + mt->offset; /* reloc */
 
-   surf->ss5.mip_count = intelObj->_MaxLevel - tObj->BaseLevel;
-   surf->ss5.min_lod = 0;
+   surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) |
+             SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT);
+   surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
+             ((intelObj->mt->region->pitch * intelObj->mt->cpp) - 1);
 
-   /* ss5 remaining fields:
-    * - x_offset (N/A for textures?)
-    * - y_offset (ditto)
-    * - cache_control
-    */
+   surf[5] = intelObj->_MaxLevel - tObj->BaseLevel; /* mip count */
 
-   if (brw->intel.is_haswell) {
+   if (intel->is_haswell) {
       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
        * texturing functions that return a float, as our code generation always
        * selects the .x channel (which would always be 0).
@@ -381,16 +348,17 @@ gen7_update_texture_surface(struct gl_context *ctx,
       const int swizzle =
          unlikely(alpha_depth) ? SWIZZLE_XYZW : brw_get_texture_swizzle(tObj);
 
-      surf->ss7.shader_channel_select_r = swizzle_to_scs(GET_SWZ(swizzle, 0));
-      surf->ss7.shader_channel_select_g = swizzle_to_scs(GET_SWZ(swizzle, 1));
-      surf->ss7.shader_channel_select_b = swizzle_to_scs(GET_SWZ(swizzle, 2));
-      surf->ss7.shader_channel_select_a = swizzle_to_scs(GET_SWZ(swizzle, 3));
+
+      surf[7] =
+         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
+         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
+         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
+         SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
    }
 
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-			   binding_table[surf_index] +
-			   offsetof(struct gen7_surface_state, ss1),
+			   binding_table[surf_index] + 4,
 			   intelObj->mt->region->bo, intelObj->mt->offset,
 			   I915_GEM_DOMAIN_SAMPLER, 0);
 
@@ -408,41 +376,38 @@ gen7_create_constant_surface(struct brw_context *brw,
 			     int width,
 			     uint32_t *out_offset)
 {
+   struct intel_context *intel = &brw->intel;
    const GLint w = width - 1;
-   struct gen7_surface_state *surf;
-
-   surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-			  sizeof(*surf), 32, out_offset);
-   memset(surf, 0, sizeof(*surf));
 
-   surf->ss0.surface_type = BRW_SURFACE_BUFFER;
-   surf->ss0.surface_format = BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
+   uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+                                    8 * 4, 32, out_offset);
+   memset(surf, 0, 8 * 4);
 
-   surf->ss0.render_cache_read_write = 1;
+   surf[0] = BRW_SURFACE_BUFFER << BRW_SURFACE_TYPE_SHIFT |
+             BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_SURFACE_FORMAT_SHIFT |
+             BRW_SURFACE_RC_READ_WRITE;
 
    assert(bo);
-   surf->ss1.base_addr = bo->offset + offset; /* reloc */
-
-   surf->ss2.width = w & 0x7f;            /* bits 6:0 of size or width */
-   surf->ss2.height = (w >> 7) & 0x1fff;  /* bits 19:7 of size or width */
-   surf->ss3.depth = (w >> 20) & 0x7f;    /* bits 26:20 of size or width */
-   surf->ss3.pitch = (16 - 1); /* stride between samples */
-   gen7_set_surface_tiling(surf, I915_TILING_NONE); /* tiling now allowed */
-
-   if (brw->intel.is_haswell) {
-      surf->ss7.shader_channel_select_r = HSW_SCS_RED;
-      surf->ss7.shader_channel_select_g = HSW_SCS_GREEN;
-      surf->ss7.shader_channel_select_b = HSW_SCS_BLUE;
-      surf->ss7.shader_channel_select_a = HSW_SCS_ALPHA;
+   surf[1] = bo->offset + offset; /* reloc */
+
+   surf[2] = SET_FIELD(w & 0x7f, GEN7_SURFACE_WIDTH) |
+             SET_FIELD((w >> 7) & 0x1fff, GEN7_SURFACE_HEIGHT);
+   surf[3] = SET_FIELD((w >> 20) & 0x7f, BRW_SURFACE_DEPTH) |
+             (16 - 1); /* stride between samples */
+
+   if (intel->is_haswell) {
+      surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
+                SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
+                SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
+                SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
    }
 
    /* Emit relocation to surface contents.  Section 5.1.1 of the gen4
     * bspec ("Data Cache") says that the data cache does not exist as
     * a separate cache and is just the sampler cache.
     */
-   drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-			   (*out_offset +
-			    offsetof(struct gen7_surface_state, ss1)),
+   drm_intel_bo_emit_reloc(intel->batch.bo,
+			   *out_offset + 4,
 			   bo, offset,
 			   I915_GEM_DOMAIN_SAMPLER, 0);
 
@@ -469,26 +434,24 @@ gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit)
     */
    struct intel_context *intel = &brw->intel;
    struct gl_context *ctx = &intel->ctx;
-   struct gen7_surface_state *surf;
 
    /* _NEW_BUFFERS */
    const struct gl_framebuffer *fb = ctx->DrawBuffer;
 
-   surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-			  sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
-   memset(surf, 0, sizeof(*surf));
-
-   surf->ss0.surface_type = BRW_SURFACE_NULL;
-   surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
-
-   surf->ss2.width = fb->Width - 1;
-   surf->ss2.height = fb->Height - 1;
+   uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+			            8 * 4, 32, &brw->wm.surf_offset[unit]);
+   memset(surf, 0, 8 * 4);
 
-   /* From the Ivy bridge PRM, Vol4 Part1 p65 (Tiled Surface: Programming Notes):
-    *
-    *     If Surface Type is SURFTYPE_NULL, this field must be TRUE.
+   /* From the Ivybridge PRM, Volume 4, Part 1, page 65,
+    * Tiled Surface: Programming Notes:
+    * "If Surface Type is SURFTYPE_NULL, this field must be TRUE."
     */
-   gen7_set_surface_tiling(surf, I915_TILING_Y);
+   surf[0] = BRW_SURFACE_NULL << BRW_SURFACE_TYPE_SHIFT |
+             BRW_SURFACEFORMAT_B8G8R8A8_UNORM << BRW_SURFACE_FORMAT_SHIFT |
+             GEN7_SURFACE_TILING_Y;
+
+   surf[2] = SET_FIELD(fb->Width - 1, GEN7_SURFACE_WIDTH) |
+             SET_FIELD(fb->Height - 1, GEN7_SURFACE_HEIGHT);
 
    gen7_check_surface_setup(surf, true /* is_render_target */);
 }
@@ -507,22 +470,17 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
    struct gl_context *ctx = &intel->ctx;
    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
    struct intel_region *region = irb->mt->region;
-   struct gen7_surface_state *surf;
    uint32_t tile_x, tile_y;
+   uint32_t format;
    gl_format rb_format = intel_rb_format(irb);
 
-   surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
-			  sizeof(*surf), 32, &brw->wm.surf_offset[unit]);
-   memset(surf, 0, sizeof(*surf));
+   uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
+                                    8 * 4, 32, &brw->wm.surf_offset[unit]);
+   memset(surf, 0, 8 * 4);
 
    /* Render targets can't use IMS layout */
    assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 
-   if (irb->mt->align_h == 4)
-      surf->ss0.vertical_alignment = 1;
-   if (irb->mt->align_w == 8)
-      surf->ss0.horizontal_alignment = 1;
-
    switch (rb_format) {
    case MESA_FORMAT_SARGB8:
       /* _NEW_BUFFERS
@@ -531,27 +489,34 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
        * blend/update as sRGB.
        */
       if (ctx->Color.sRGBEnabled)
-	 surf->ss0.surface_format = brw_format_for_mesa_format(rb_format);
+	 format = brw_format_for_mesa_format(rb_format);
       else
-	 surf->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
+	 format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
       break;
    default:
       assert(brw_render_target_supported(intel, rb));
-      surf->ss0.surface_format = brw->render_target_format[rb_format];
+      format = brw->render_target_format[rb_format];
       if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
 	 _mesa_problem(ctx, "%s: renderbuffer format %s unsupported\n",
 		       __FUNCTION__, _mesa_get_format_name(rb_format));
       }
-       break;
+      break;
    }
 
-   surf->ss0.surface_type = BRW_SURFACE_2D;
-   surf->ss0.surface_array_spacing = irb->mt->array_spacing_lod0 ?
-      GEN7_SURFACE_ARYSPC_LOD0 : GEN7_SURFACE_ARYSPC_FULL;
+   surf[0] = BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT |
+             format << BRW_SURFACE_FORMAT_SHIFT |
+             (irb->mt->array_spacing_lod0 ? GEN7_SURFACE_ARYSPC_LOD0
+                                          : GEN7_SURFACE_ARYSPC_FULL) |
+             gen7_surface_tiling_mode(region->tiling);
+
+   if (irb->mt->align_h == 4)
+      surf[0] |= GEN7_SURFACE_VALIGN_4;
+   if (irb->mt->align_w == 8)
+      surf[0] |= GEN7_SURFACE_HALIGN_8;
 
    /* reloc */
-   surf->ss1.base_addr = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y);
-   surf->ss1.base_addr += region->bo->offset; /* reloc */
+   surf[1] = intel_renderbuffer_tile_offsets(irb, &tile_x, &tile_y) +
+             region->bo->offset; /* reloc */
 
    assert(brw->has_surface_tile_offset);
    /* Note that the low bits of these fields are missing, so
@@ -559,33 +524,31 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
     */
    assert(tile_x % 4 == 0);
    assert(tile_y % 2 == 0);
-   surf->ss5.x_offset = tile_x / 4;
-   surf->ss5.y_offset = tile_y / 2;
+   surf[5] = SET_FIELD(tile_x / 4, BRW_SURFACE_X_OFFSET) |
+             SET_FIELD(tile_y / 2, BRW_SURFACE_Y_OFFSET);
 
-   surf->ss2.width = rb->Width - 1;
-   surf->ss2.height = rb->Height - 1;
-   gen7_set_surface_tiling(surf, region->tiling);
-   surf->ss3.pitch = (region->pitch * region->cpp) - 1;
+   surf[2] = SET_FIELD(rb->Width - 1, GEN7_SURFACE_WIDTH) |
+             SET_FIELD(rb->Height - 1, GEN7_SURFACE_HEIGHT);
+   surf[3] = (region->pitch * region->cpp) - 1;
 
-   gen7_set_surface_msaa(surf, irb->mt->num_samples, irb->mt->msaa_layout);
+   surf[4] = gen7_surface_msaa_bits(irb->mt->num_samples, irb->mt->msaa_layout);
 
    if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
       gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit],
-                                irb->mt->mcs_mt, true /* is_render_target */);
+                                irb->mt->mcs_mt, true /* is RT */);
    }
 
    if (intel->is_haswell) {
-      surf->ss7.shader_channel_select_r = HSW_SCS_RED;
-      surf->ss7.shader_channel_select_g = HSW_SCS_GREEN;
-      surf->ss7.shader_channel_select_b = HSW_SCS_BLUE;
-      surf->ss7.shader_channel_select_a = HSW_SCS_ALPHA;
+      surf[7] = SET_FIELD(HSW_SCS_RED,   GEN7_SURFACE_SCS_R) |
+                SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) |
+                SET_FIELD(HSW_SCS_BLUE,  GEN7_SURFACE_SCS_B) |
+                SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A);
    }
 
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,
-			   brw->wm.surf_offset[unit] +
-			   offsetof(struct gen7_surface_state, ss1),
+			   brw->wm.surf_offset[unit] + 4,
 			   region->bo,
-			   surf->ss1.base_addr - region->bo->offset,
+			   surf[1] - region->bo->offset,
 			   I915_GEM_DOMAIN_RENDER,
 			   I915_GEM_DOMAIN_RENDER);