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| author | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2015-03-17 13:09:16 +0200 |
|---|---|---|
| committer | Topi Pohjolainen <topi.pohjolainen@intel.com> | 2015-04-30 00:28:47 +0300 |
| commit | c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea (patch) | |
| tree | ccd48e3f6822bb113da13ebe912beea2041774dd /src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | |
| parent | d6c83c9d863f9f13e46584b93cbab6d3a3885aea (diff) | |
| download | external_mesa3d-c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea.zip external_mesa3d-c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea.tar.gz external_mesa3d-c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea.tar.bz2 | |
i965: Refactor rb surface setup to allow caller to store offsets
Notice that in gen7_wm_surface_state.c there is also indentation
change in the surrounding code removing tabs.
v2 (Matt): Fixed whitespace: tabs -> spaces
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_surface_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 4b8503c..15ab2b0 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -448,11 +448,11 @@ gen7_emit_null_surface_state(struct brw_context *brw, * While it is only used for the front/back buffer currently, it should be * usable for further buffers when doing ARB_draw_buffer support. */ -static void +static uint32_t gen7_update_renderbuffer_surface(struct brw_context *brw, - struct gl_renderbuffer *rb, - bool layered, - unsigned int unit) + struct gl_renderbuffer *rb, + bool layered, unsigned unit /* unused */, + uint32_t surf_index) { struct gl_context *ctx = &brw->ctx; struct intel_renderbuffer *irb = intel_renderbuffer(rb); @@ -464,17 +464,15 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, bool is_array = false; int depth = MAX2(irb->layer_count, 1); const uint8_t mocs = GEN7_MOCS_L3; + uint32_t offset; int min_array_element = irb->mt_layer / MAX2(mt->num_samples, 1); GLenum gl_target = rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; - uint32_t surf_index = - brw->wm.prog_data->binding_table.render_target_start + unit; - uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, - &brw->wm.base.surf_offset[surf_index]); + &offset); memset(surf, 0, 8 * 4); intel_miptree_used_for_rendering(irb->mt); @@ -539,7 +537,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT; if (irb->mt->mcs_mt) { - gen7_set_surface_mcs_info(brw, surf, brw->wm.base.surf_offset[surf_index], + gen7_set_surface_mcs_info(brw, surf, offset, irb->mt->mcs_mt, true /* is RT */); } @@ -553,13 +551,15 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, } drm_intel_bo_emit_reloc(brw->batch.bo, - brw->wm.base.surf_offset[surf_index] + 4, - mt->bo, - surf[1] - mt->bo->offset64, - I915_GEM_DOMAIN_RENDER, - I915_GEM_DOMAIN_RENDER); + offset + 4, + mt->bo, + surf[1] - mt->bo->offset64, + I915_GEM_DOMAIN_RENDER, + I915_GEM_DOMAIN_RENDER); gen7_check_surface_setup(surf, true /* is_render_target */); + + return offset; } void |