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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-08-12 16:07:08 +0300 |
|---|---|---|
| committer | Chad Versace <chad.versace@linux.intel.com> | 2013-08-21 10:14:04 -0700 |
| commit | e6893b99adcd6d9fb1bd49067883f66cc5603fe7 (patch) | |
| tree | 911dcf8c97d0cfb929ac509216f5f4a6aa149c2c /src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | |
| parent | 22161983c38fe19b393e5b983f4945dc527ccb1b (diff) | |
| download | external_mesa3d-e6893b99adcd6d9fb1bd49067883f66cc5603fe7.zip external_mesa3d-e6893b99adcd6d9fb1bd49067883f66cc5603fe7.tar.gz external_mesa3d-e6893b99adcd6d9fb1bd49067883f66cc5603fe7.tar.bz2 | |
i965/gen7: Set MOCS L3 cacheability for IVB/BYT (v2)
IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
so let's make use of it.
pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most
other things show less gains/no regressions, except furmark which
loses some 10 points.
I didn't have a BYT at hand for testing.
v2: Don't check (brw->gen == 7) in gen7 functions. (chadv)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen7_wm_surface_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index cdd2242..91f854b 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -286,7 +286,6 @@ gen7_update_texture_surface(struct gl_context *ctx, struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); uint32_t tile_x, tile_y; - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; if (tObj->Target == GL_TEXTURE_BUFFER) { gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); @@ -335,7 +334,7 @@ gen7_update_texture_surface(struct gl_context *ctx, */ surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | - SET_FIELD(mocs, GEN7_SURFACE_MOCS) | + SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) | /* mip count */ (intelObj->_MaxLevel - tObj->BaseLevel)); @@ -514,7 +513,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, bool is_array = false; int depth = MAX2(rb->Depth, 1); int min_array_element; - uint8_t mocs = brw->is_haswell ? GEN7_MOCS_L3 : 0; + const uint8_t mocs = GEN7_MOCS_L3; GLenum gl_target = rb->TexImage ? rb->TexImage->TexObject->Target : GL_TEXTURE_2D; |