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| author | Kenneth Graunke <kenneth@whitecape.org> | 2014-03-04 16:30:28 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2014-03-25 15:14:08 -0700 |
| commit | ee4484be3dc827cf15bcf109f5e680dbf1dfbf34 (patch) | |
| tree | 7109825c6c2314f893abca7efc7d06db8706140f /src/mesa/drivers/dri/i965/gen8_depth_state.c | |
| parent | 1afe3359258a9e89b62c8638761f52d78f6d1cbc (diff) | |
| download | external_mesa3d-ee4484be3dc827cf15bcf109f5e680dbf1dfbf34.zip external_mesa3d-ee4484be3dc827cf15bcf109f5e680dbf1dfbf34.tar.gz external_mesa3d-ee4484be3dc827cf15bcf109f5e680dbf1dfbf34.tar.bz2 | |
i965: Set Broadwell MOCS values everywhere it's possible.
This patch introduces two pre-canned MOCS values: BDW_MOCS_WB
(write-back, all caches) and BDW_MOCS_WT (write-through, all caches).
We use write-through caching for render targets, and write-back for
all other data. (At least on Haswell, I believe write-back LLC/eLLC
didn't work for scan-out buffers, while write-through did.)
No performance analysis has been done on the impact of this patch.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen8_depth_state.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen8_depth_state.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c index 379a2c3..621951e 100644 --- a/src/mesa/drivers/dri/i965/gen8_depth_state.c +++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c @@ -68,7 +68,7 @@ emit_depth_packets(struct brw_context *brw, OUT_BATCH(0); } OUT_BATCH(((width - 1) << 4) | ((height - 1) << 18) | lod); - OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10)); + OUT_BATCH(((depth - 1) << 21) | (min_array_element << 10) | BDW_MOCS_WB); OUT_BATCH(0); OUT_BATCH(depth_mt ? depth_mt->qpitch >> 2 : 0); ADVANCE_BATCH(); @@ -84,7 +84,7 @@ emit_depth_packets(struct brw_context *brw, } else { BEGIN_BATCH(5); OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (5 - 2)); - OUT_BATCH(depth_mt->hiz_mt->region->pitch - 1); + OUT_BATCH((depth_mt->hiz_mt->region->pitch - 1) | BDW_MOCS_WB << 25); OUT_RELOC64(depth_mt->hiz_mt->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); OUT_BATCH(depth_mt->hiz_mt->qpitch >> 2); @@ -116,7 +116,8 @@ emit_depth_packets(struct brw_context *brw, * page (which would imply that it does). Experiments with the hardware * indicate that it does. */ - OUT_BATCH(HSW_STENCIL_ENABLED | (2 * stencil_mt->region->pitch - 1)); + OUT_BATCH(HSW_STENCIL_ENABLED | BDW_MOCS_WB << 22 | + (2 * stencil_mt->region->pitch - 1)); OUT_RELOC64(stencil_mt->region->bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, stencil_offset); |