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author | Kristian Høgsberg <krh@bitplanet.net> | 2014-07-07 16:27:31 -0700 |
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committer | Kristian Høgsberg <krh@bitplanet.net> | 2014-08-15 10:33:41 -0700 |
commit | cf89b29d2f87be8ca437049e5cf3df9f54a806b2 (patch) | |
tree | 663193c7a704f14713820c48150e93a86f383f6e /src/mesa/drivers/dri/i965/gen8_ps_state.c | |
parent | 1a05dcb349514ba3287cdfec89db9ddf951aaae8 (diff) | |
download | external_mesa3d-cf89b29d2f87be8ca437049e5cf3df9f54a806b2.zip external_mesa3d-cf89b29d2f87be8ca437049e5cf3df9f54a806b2.tar.gz external_mesa3d-cf89b29d2f87be8ca437049e5cf3df9f54a806b2.tar.bz2 |
i965: Provide a context flag to let us enable fast clear
GEN7+ has the fast clear functionality, which lets us clear the color
buffers using the MCS and a scaled down rectangle. To enable this
we have to set the appropriate bits in the 3DSTATE_PS package.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/gen8_ps_state.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/gen8_ps_state.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c b/src/mesa/drivers/dri/i965/gen8_ps_state.c index 49d4fe0..5e313bf 100644 --- a/src/mesa/drivers/dri/i965/gen8_ps_state.c +++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c @@ -185,6 +185,8 @@ upload_ps_state(struct brw_context *brw) else dw6 |= GEN7_PS_POSOFFSET_NONE; + dw6 |= brw->wm.fast_clear_op; + /* _NEW_MULTISAMPLE * In case of non 1x per sample shading, only one of SIMD8 and SIMD16 * should be enabled. We do 'SIMD16 only' dispatch if a SIMD16 shader |