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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-02-26 23:01:33 -0800 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-03-02 19:28:43 -0800 |
| commit | 37c2687645bf44515dbd1bc1c066b02889ca46c4 (patch) | |
| tree | 2b51591fb4219be3aca3b9911b9ffe8e4bcedb34 /src/mesa/drivers/dri/i965/intel_batchbuffer.c | |
| parent | e214000f258ae564e64d839cccee9418526f226b (diff) | |
| download | external_mesa3d-37c2687645bf44515dbd1bc1c066b02889ca46c4.zip external_mesa3d-37c2687645bf44515dbd1bc1c066b02889ca46c4.tar.gz external_mesa3d-37c2687645bf44515dbd1bc1c066b02889ca46c4.tar.bz2 | |
i965: Rename some PIPE_CONTROL flags
I'm not really sure of the origins of the existing flag names. Modern docs have
some slightly different names. Having the correct names makes it easier to
determine if existing PIPE_CONTROL flag settings are correct, as well as making
adding new PIPE_CONTROLs easier.
This originally came up while I was trying to implement workarounds and spotted
some things called, "flush" which should have been called "invalidate."
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_batchbuffer.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 45c7493..5ac4d18 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -411,7 +411,7 @@ intel_batchbuffer_data(struct brw_context *brw, static void gen8_add_cs_stall_workaround_bits(uint32_t *flags) { - uint32_t wa_bits = PIPE_CONTROL_WRITE_FLUSH | + uint32_t wa_bits = PIPE_CONTROL_RENDER_TARGET_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_WRITE_IMMEDIATE | PIPE_CONTROL_WRITE_DEPTH_COUNT | @@ -665,7 +665,7 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw) OUT_BATCH(0); ADVANCE_BATCH(); } else { - int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_WRITE_FLUSH; + int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; if (brw->gen >= 6) { if (brw->gen == 9) { /* Hardware workaround: SKL @@ -676,10 +676,10 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw) brw_emit_pipe_control_flush(brw, 0); } - flags |= PIPE_CONTROL_INSTRUCTION_FLUSH | + flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_VF_CACHE_INVALIDATE | - PIPE_CONTROL_TC_FLUSH | + PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CS_STALL; if (brw->gen == 6) { |