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| author | Kenneth Graunke <kenneth@whitecape.org> | 2013-10-28 16:06:10 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2013-11-21 15:01:13 -0800 |
| commit | 6bc40f9af5b35724caff9fa7ced47b2ca6183f22 (patch) | |
| tree | b998c16cdaafcea8ce8f20f9f056dd9408e26380 /src/mesa/drivers/dri/i965/intel_batchbuffer.c | |
| parent | 28d7b4147d4048031dd1a99c0858472912ea7e7e (diff) | |
| download | external_mesa3d-6bc40f9af5b35724caff9fa7ced47b2ca6183f22.zip external_mesa3d-6bc40f9af5b35724caff9fa7ced47b2ca6183f22.tar.gz external_mesa3d-6bc40f9af5b35724caff9fa7ced47b2ca6183f22.tar.bz2 | |
i965: Convert brw->batch.is_blit to a BLT_RING/RENDER_RING enum.
Passing BLT_RING or RENDER_RING to batchbuffer functions is a lot more
obvious than passing true or false.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_batchbuffer.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index babe9ea..672bc02 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -260,19 +260,18 @@ do_flush_locked(struct brw_context *brw) if (!brw->intelScreen->no_hw) { int flags; - if (brw->gen < 6 || !batch->is_blit) { - flags = I915_EXEC_RENDER; + if (brw->gen >= 6 && batch->ring == BLT_RING) { + flags = I915_EXEC_BLT; } else { - flags = I915_EXEC_BLT; + flags = I915_EXEC_RENDER; } - if (batch->needs_sol_reset) flags |= I915_EXEC_GEN7_SOL_RESET; if (ret == 0) { if (unlikely(INTEL_DEBUG & DEBUG_AUB)) brw_annotate_aub(brw); - if (brw->hw_ctx == NULL || batch->is_blit) { + if (brw->hw_ctx == NULL || batch->ring != RENDER_RING) { ret = drm_intel_bo_mrb_exec(batch->bo, 4 * batch->used, NULL, 0, 0, flags); } else { @@ -401,10 +400,10 @@ intel_batchbuffer_emit_reloc_fenced(struct brw_context *brw, void intel_batchbuffer_data(struct brw_context *brw, - const void *data, GLuint bytes, bool is_blit) + const void *data, GLuint bytes, enum brw_gpu_ring ring) { assert((bytes & 3) == 0); - intel_batchbuffer_require_space(brw, bytes, is_blit); + intel_batchbuffer_require_space(brw, bytes, ring); __memcpy(brw->batch.map + brw->batch.used, data, bytes); brw->batch.used += bytes >> 2; } @@ -613,7 +612,7 @@ void intel_batchbuffer_emit_mi_flush(struct brw_context *brw) { if (brw->gen >= 6) { - if (brw->batch.is_blit) { + if (brw->batch.ring == BLT_RING) { BEGIN_BATCH_BLT(4); OUT_BATCH(MI_FLUSH_DW); OUT_BATCH(0); |