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author | Jordan Justen <jordan.l.justen@intel.com> | 2016-04-17 13:08:01 -0700 |
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committer | Jordan Justen <jordan.l.justen@intel.com> | 2016-05-04 11:23:10 -0700 |
commit | c54e5c2fb22795bcce1ff18f2a0a70d6a4c647a4 (patch) | |
tree | 725b0ed6b832f6a00a456544fc9bdcb319727051 /src/mesa/drivers/dri/i965/intel_batchbuffer.c | |
parent | 77959ce07b75f83bff2aae30e4e78aa3c50ab70f (diff) | |
download | external_mesa3d-c54e5c2fb22795bcce1ff18f2a0a70d6a4c647a4.zip external_mesa3d-c54e5c2fb22795bcce1ff18f2a0a70d6a4c647a4.tar.gz external_mesa3d-c54e5c2fb22795bcce1ff18f2a0a70d6a4c647a4.tar.bz2 |
i965: Use offset instead of index in brw_store_register_mem64
This matches the byte based offset of brw_load_register_mem*.
The function is also moved into intel_batchbuffer.c like
brw_load_register_mem*.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_batchbuffer.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index e41f927..cd5d301 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -537,3 +537,40 @@ brw_load_register_mem64(struct brw_context *brw, { load_sized_register_mem(brw, reg, bo, read_domains, write_domain, offset, 2); } + +/* + * Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM. + */ +void +brw_store_register_mem64(struct brw_context *brw, + drm_intel_bo *bo, uint32_t reg, uint32_t offset) +{ + assert(brw->gen >= 6); + + /* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to + * read a full 64-bit register, we need to do two of them. + */ + if (brw->gen >= 8) { + BEGIN_BATCH(8); + OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); + OUT_BATCH(reg); + OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + offset); + OUT_BATCH(MI_STORE_REGISTER_MEM | (4 - 2)); + OUT_BATCH(reg + sizeof(uint32_t)); + OUT_RELOC64(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + offset + sizeof(uint32_t)); + ADVANCE_BATCH(); + } else { + BEGIN_BATCH(6); + OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); + OUT_BATCH(reg); + OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + offset); + OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2)); + OUT_BATCH(reg + sizeof(uint32_t)); + OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, + offset + sizeof(uint32_t)); + ADVANCE_BATCH(); + } +} |