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| author | Kenneth Graunke <kenneth@whitecape.org> | 2016-05-04 22:52:52 -0700 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2016-05-09 15:00:01 -0700 |
| commit | fdb6c1887f7b61ef49fb89e0b0928f65b2edf29b (patch) | |
| tree | e51ac72b01333975bee71a317c14712388dac88a /src/mesa/drivers/dri/i965/intel_batchbuffer.c | |
| parent | 4c71c8a74ad29bd84ca16803672ad1e9e30e2fff (diff) | |
| download | external_mesa3d-fdb6c1887f7b61ef49fb89e0b0928f65b2edf29b.zip external_mesa3d-fdb6c1887f7b61ef49fb89e0b0928f65b2edf29b.tar.gz external_mesa3d-fdb6c1887f7b61ef49fb89e0b0928f65b2edf29b.tar.bz2 | |
i965: Add a brw_load_register_reg64 helper.
It appears that we can't do this in a single command (like we do for
MI_LOAD_REGISTER_IMM) - the Skylake simulator gets rather grumpy about
the command length if I try to combine them. No matter.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_batchbuffer.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 98b9485..77cdc0a 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -649,6 +649,24 @@ brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest) } /* + * Copies a 64-bit register. + */ +void +brw_load_register_reg64(struct brw_context *brw, uint32_t src, uint32_t dest) +{ + assert(brw->gen >= 8 || brw->is_haswell); + + BEGIN_BATCH(6); + OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2)); + OUT_BATCH(src); + OUT_BATCH(dest); + OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2)); + OUT_BATCH(src + sizeof(uint32_t)); + OUT_BATCH(dest + sizeof(uint32_t)); + ADVANCE_BATCH(); +} + +/* * Write 32-bits of immediate data to a GPU memory buffer. */ void |