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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-07-09 10:35:19 -0700 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-07-09 11:11:06 -0700 |
| commit | 0166b4c165271bd7525a91049e58e390cb596c60 (patch) | |
| tree | 88fce6beeae764373e2596aa19691bf4e3bb0057 /src/mesa/drivers/dri/i965/intel_batchbuffer.h | |
| parent | 2cfa64e159a68998b76bdbcd20f8c7810379fce0 (diff) | |
| download | external_mesa3d-0166b4c165271bd7525a91049e58e390cb596c60.zip external_mesa3d-0166b4c165271bd7525a91049e58e390cb596c60.tar.gz external_mesa3d-0166b4c165271bd7525a91049e58e390cb596c60.tar.bz2 | |
i965/hsw: Implement end of batch workaround
This patch can cause an infinite recursion if the previous patch titled, "i965:
Track finished batch state" isn't present (backporters take notice).
v2: Sent out the wrong patch originally. This patches switches the order of
flushes, doing the generic flush before the CC_STATE, and the required
workaround flush afterwards
v3: Only perform workaround for render ring
Add text to the BATCH_RESERVE comments
v4 (By Ken): Rebase; update citation to mention PRM and Wa name; combine two
blocks.
http://otc-mesa-ci.jf.intel.com/job/bwidawsk/171/
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_batchbuffer.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h index fdd07e0..8eaedd1 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h @@ -26,6 +26,10 @@ extern "C" { * - 3 DWords for MI_REPORT_PERF_COUNT itself on Gen6+. ==> 12 bytes. * On Ironlake, it's 6 DWords, but we have some slack due to the lack of * Sandybridge PIPE_CONTROL madness. + * - CC_STATE workaround on HSW (12 * 4 = 48 bytes) + * - 5 dwords for initial mi_flush + * - 2 dwords for CC state setup + * - 5 dwords for the required pipe control at the end */ #define BATCH_RESERVED 152 |