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author | Kenneth Graunke <kenneth@whitecape.org> | 2013-11-04 16:55:26 -0800 |
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committer | Kenneth Graunke <kenneth@whitecape.org> | 2014-01-20 15:12:23 -0800 |
commit | f11c1feaf7a92d5109bcc86efaefec3a0193766a (patch) | |
tree | 3efba085d8960322ac2a2a5395e18336002abcf2 /src/mesa/drivers/dri/i965/intel_batchbuffer.h | |
parent | 67ebcb4711d7c6d35df03298f065806613a62798 (diff) | |
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i965: Introduce an OUT_RELOC64 macro.
Broadwell uses 48-bit addresses. The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_batchbuffer.h')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h index eff03b3..2b2693f 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h @@ -59,6 +59,11 @@ bool intel_batchbuffer_emit_reloc(struct brw_context *brw, uint32_t read_domains, uint32_t write_domain, uint32_t offset); +bool intel_batchbuffer_emit_reloc64(struct brw_context *brw, + drm_intel_bo *buffer, + uint32_t read_domains, + uint32_t write_domain, + uint32_t offset); void intel_batchbuffer_emit_mi_flush(struct brw_context *brw); void intel_emit_post_sync_nonzero_flush(struct brw_context *brw); void intel_emit_depth_stall_flushes(struct brw_context *brw); @@ -167,6 +172,11 @@ intel_batchbuffer_advance(struct brw_context *brw) read_domains, write_domain, delta); \ } while (0) +/* Handle 48-bit address relocations for Gen8+ */ +#define OUT_RELOC64(buf, read_domains, write_domain, delta) do { \ + intel_batchbuffer_emit_reloc64(brw, buf, read_domains, write_domain, delta); \ +} while (0) + #define ADVANCE_BATCH() intel_batchbuffer_advance(brw); #ifdef __cplusplus |