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author | Kenneth Graunke <kenneth@whitecape.org> | 2014-01-13 16:00:18 -0800 |
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committer | Kenneth Graunke <kenneth@whitecape.org> | 2014-01-20 15:38:23 -0800 |
commit | f5dd608db2d6a67cfe27efed948408414a057fe3 (patch) | |
tree | 6176e8df8ae38ba9b23b2b168214158f40aa23ad /src/mesa/drivers/dri/i965/intel_batchbuffer.h | |
parent | 35458a99c0940ec29503fa02134ec3ed9de363f9 (diff) | |
download | external_mesa3d-f5dd608db2d6a67cfe27efed948408414a057fe3.zip external_mesa3d-f5dd608db2d6a67cfe27efed948408414a057fe3.tar.gz external_mesa3d-f5dd608db2d6a67cfe27efed948408414a057fe3.tar.bz2 |
i965: Create a helper function for emitting PIPE_CONTROL writes.
There are a lot of places that use PIPE_CONTROL to write a value to a
buffer (either an immediate write, TIMESTAMP, or PS_DEPTH_COUNT).
Creating a single function to do this seems convenient.
As part of this refactor, we now set the PPGTT/GTT selection bit
correctly on Gen7+. Previously, we set bit 2 of DW2 on all platforms.
This is correct for Sandybridge, but actually part of the address on
Ivybridge and later!
Broadwell will also increase the length of these packets by 1; with the
refactoring, we should have to adjust that in substantially fewer
places, giving us confidence that we've hit them all.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_batchbuffer.h')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.h b/src/mesa/drivers/dri/i965/intel_batchbuffer.h index 5ed2089..779a7cc 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.h @@ -65,6 +65,9 @@ bool intel_batchbuffer_emit_reloc64(struct brw_context *brw, uint32_t write_domain, uint32_t offset); void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags); +void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, + drm_intel_bo *bo, uint32_t offset, + uint32_t imm_lower, uint32_t imm_upper); void intel_batchbuffer_emit_mi_flush(struct brw_context *brw); void intel_emit_post_sync_nonzero_flush(struct brw_context *brw); void intel_emit_depth_stall_flushes(struct brw_context *brw); |