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| author | Anuj Phogat <anuj.phogat@gmail.com> | 2015-08-11 16:31:39 -0700 |
|---|---|---|
| committer | Anuj Phogat <anuj.phogat@gmail.com> | 2015-09-28 12:43:43 -0700 |
| commit | 0fa39bff19dc2fbd3c184bd0e1267c86bd5040d9 (patch) | |
| tree | 12678585b70f7095965349ee36fb95467f23f15d /src/mesa/drivers/dri/i965/intel_blit.c | |
| parent | e83b07aa7b124184decd68a64d970e8f408f8725 (diff) | |
| download | external_mesa3d-0fa39bff19dc2fbd3c184bd0e1267c86bd5040d9.zip external_mesa3d-0fa39bff19dc2fbd3c184bd0e1267c86bd5040d9.tar.gz external_mesa3d-0fa39bff19dc2fbd3c184bd0e1267c86bd5040d9.tar.bz2 | |
i965: Fix {src, dst}_pitch alignment check for XY_SRC_COPY_BLT
Current code checks the alignment restrictions only for Y tiling.
From Broadwell PRM vol 10:
"pitch is of 512Byte granularity for Tile-X: This means the tiled-x
surface pitch can be (512, 1024, 1536, 2048...)/4 (in Dwords)."
This patch adds the restriction for X tiling as well.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_blit.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 8bb4120..0cd2a20 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -522,6 +522,8 @@ intelEmitCopyBlit(struct brw_context *brw, bool dst_y_tiled = dst_tiling == I915_TILING_Y; bool src_y_tiled = src_tiling == I915_TILING_Y; bool use_fast_copy_blit = false; + uint32_t src_tile_w, src_tile_h; + uint32_t dst_tile_w, dst_tile_h; if ((dst_y_tiled || src_y_tiled) && brw->gen < 6) return false; @@ -550,6 +552,9 @@ intelEmitCopyBlit(struct brw_context *brw, src_buffer, src_pitch, src_offset, src_x, src_y, dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); + intel_get_tile_dims(src_tiling, src_tr_mode, cpp, &src_tile_w, &src_tile_h); + intel_get_tile_dims(dst_tiling, dst_tr_mode, cpp, &dst_tile_w, &dst_tile_h); + use_fast_copy_blit = can_fast_copy_blit(brw, src_buffer, src_x, src_y, @@ -588,8 +593,8 @@ intelEmitCopyBlit(struct brw_context *brw, cpp, use_fast_copy_blit); } else { - assert(!dst_y_tiled || (dst_pitch % 128) == 0); - assert(!src_y_tiled || (src_pitch % 128) == 0); + assert(src_tiling == I915_TILING_NONE || (src_pitch % src_tile_w) == 0); + assert(dst_tiling == I915_TILING_NONE || (dst_pitch % dst_tile_w) == 0); /* For big formats (such as floating point), do the copy using 16 or * 32bpp and multiply the coordinates. |