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| author | Eric Anholt <eric@anholt.net> | 2014-02-25 14:25:46 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2014-03-14 12:56:22 -0700 |
| commit | 2f879356b552ad75bebbafc8d4bc1c97834b8b79 (patch) | |
| tree | 1a74df64b6e2d4eccf72ce8f1ced377144e6609c /src/mesa/drivers/dri/i965/intel_buffer_objects.c | |
| parent | 1990da2568a0da79c6011bd83e7f7fb8bb099827 (diff) | |
| download | external_mesa3d-2f879356b552ad75bebbafc8d4bc1c97834b8b79.zip external_mesa3d-2f879356b552ad75bebbafc8d4bc1c97834b8b79.tar.gz external_mesa3d-2f879356b552ad75bebbafc8d4bc1c97834b8b79.tar.bz2 | |
i965: Add support for GL_ARB_buffer_storage.
It turns out we can allow COHERENT storage/mappings all the time,
regardless of LLC vs non-LLC. It just means never using temporary
mappings to avoid GPU stalls, and on non-LLC we have to use the GTT intead
of CPU mappings. If we were to use CPU maps on non-LLC (which might be
useful if apps end up using buffer_storage on PBO reads, to avoid WC read
slowness), those would be PERSISTENT but not COHERENT, but doing that
would require us driving the clflushes from userspace somehow.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_buffer_objects.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_buffer_objects.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c index 260308a..96dacde 100644 --- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c @@ -401,8 +401,12 @@ intel_bufferobj_map_range(struct gl_context * ctx, * doesn't require the current contents of that range, make a new * BO, and we'll copy what they put in there out at unmap or * FlushRange time. + * + * That is, unless they're looking for a persistent mapping -- we would + * need to do blits in the MemoryBarrier call, and it's easier to just do a + * GPU stall and do a mapping. */ - if (!(access & GL_MAP_UNSYNCHRONIZED_BIT) && + if (!(access & (GL_MAP_UNSYNCHRONIZED_BIT | GL_MAP_PERSISTENT_BIT)) && (access & GL_MAP_INVALIDATE_RANGE_BIT) && drm_intel_bo_busy(intel_obj->buffer)) { /* Ensure that the base alignment of the allocation meets the alignment @@ -429,7 +433,8 @@ intel_bufferobj_map_range(struct gl_context * ctx, if (access & GL_MAP_UNSYNCHRONIZED_BIT) drm_intel_gem_bo_map_unsynchronized(intel_obj->buffer); - else if (!brw->has_llc && !(access & GL_MAP_READ_BIT)) { + else if (!brw->has_llc && (!(access & GL_MAP_READ_BIT) || + (access & GL_MAP_PERSISTENT_BIT))) { drm_intel_gem_bo_map_gtt(intel_obj->buffer); intel_bufferobj_mark_inactive(intel_obj); } else { |