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| author | Eric Anholt <eric@anholt.net> | 2014-02-25 12:15:31 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2014-03-14 12:56:21 -0700 |
| commit | ea93246c009178b54848a7814a172164cd33d3c7 (patch) | |
| tree | 0e7ee83ba98781bf9cc72a81cce38365b7a3e13b /src/mesa/drivers/dri/i965/intel_buffer_objects.c | |
| parent | ff1e850eec7a18d2cc5984848977112f3c4ad4cf (diff) | |
| download | external_mesa3d-ea93246c009178b54848a7814a172164cd33d3c7.zip external_mesa3d-ea93246c009178b54848a7814a172164cd33d3c7.tar.gz external_mesa3d-ea93246c009178b54848a7814a172164cd33d3c7.tar.bz2 | |
i965: Switch mapping modes for non-explicit-flush blit-temporary maps.
On LLC, it should always be better to use a cached mapping than the GTT.
On non-LLC, it seems pretty silly to try to optimize read performance for
the INVALIDATE_RANGE_BIT case. This will make the buffer_storage logic
easier.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_buffer_objects.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_buffer_objects.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c index e6124dc..5bf4533 100644 --- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c @@ -421,11 +421,11 @@ intel_bufferobj_map_range(struct gl_context * ctx, "range map", length + extra, alignment); - if (!(access & GL_MAP_READ_BIT)) { - drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo[index]); - } else { + if (brw->has_llc) { drm_intel_bo_map(intel_obj->range_map_bo[index], (access & GL_MAP_WRITE_BIT) != 0); + } else { + drm_intel_gem_bo_map_gtt(intel_obj->range_map_bo[index]); } obj->Mappings[index].Pointer = intel_obj->range_map_bo[index]->virtual + extra; |