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| author | Francisco Jerez <currojerez@riseup.net> | 2016-06-30 19:39:24 -0700 |
|---|---|---|
| committer | Francisco Jerez <currojerez@riseup.net> | 2016-07-07 14:16:38 -0700 |
| commit | 04f74d66293222d5e1905cfb930bfa083e30463c (patch) | |
| tree | 1be8527c4f7def04546497fd77cc847bbe02296c /src/mesa/drivers/dri/i965/intel_fbo.c | |
| parent | 8fd5779da44cd6bf822a52339f3772581aa1e312 (diff) | |
| download | external_mesa3d-04f74d66293222d5e1905cfb930bfa083e30463c.zip external_mesa3d-04f74d66293222d5e1905cfb930bfa083e30463c.tar.gz external_mesa3d-04f74d66293222d5e1905cfb930bfa083e30463c.tar.bz2 | |
i965: Emit SNB write cache flush W/A from brw_emit_pipe_control_flush.
Shouldn't cause any functional changes at this point, but we have
forgotten to apply this workaround several times in the past, make
sure it doesn't happen again.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_fbo.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_fbo.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 939f9a0..707a9d2 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++ b/src/mesa/drivers/dri/i965/intel_fbo.c @@ -1061,14 +1061,6 @@ brw_render_cache_set_check_flush(struct brw_context *brw, drm_intel_bo *bo) return; if (brw->gen >= 6) { - if (brw->gen == 6) { - /* [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache - * Flush Enable = 1, a PIPE_CONTROL with any non-zero - * post-sync-op is required. - */ - brw_emit_post_sync_nonzero_flush(brw); - } - brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_RENDER_TARGET_FLUSH | |