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author | Chad Versace <chad.versace@intel.com> | 2015-10-01 07:31:31 -0700 |
---|---|---|
committer | Chad Versace <chad.versace@intel.com> | 2015-10-05 11:10:11 -0700 |
commit | 125a04b474d4a07fec892e00fd56340e7d4ab03b (patch) | |
tree | 291c7b515a27c44e1ec9c1eb1a994bd3308847f9 /src/mesa/drivers/dri/i965/intel_mipmap_tree.c | |
parent | 73e0dfbaca2fd334fd3505412bf0d38054affd25 (diff) | |
download | external_mesa3d-125a04b474d4a07fec892e00fd56340e7d4ab03b.zip external_mesa3d-125a04b474d4a07fec892e00fd56340e7d4ab03b.tar.gz external_mesa3d-125a04b474d4a07fec892e00fd56340e7d4ab03b.tar.bz2 |
i965/mt: Declare some functions as static
intel_tiling_supports_non_msrt_mcs() and
intel_miptree_is_fast_clear_capable() are not used outside of
intel_mipmap_tree.c.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_mipmap_tree.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index ffc356c..05dc291 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -160,7 +160,7 @@ intel_get_non_msrt_mcs_alignment(struct intel_mipmap_tree *mt, } } -bool +static bool intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling) { /* From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render @@ -193,7 +193,7 @@ intel_tiling_supports_non_msrt_mcs(struct brw_context *brw, unsigned tiling) * - MCS buffer for non-MSRT is supported only for RT formats 32bpp, * 64bpp, and 128bpp. */ -bool +static bool intel_miptree_is_fast_clear_capable(struct brw_context *brw, struct intel_mipmap_tree *mt) { |