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author | Anuj Phogat <anuj.phogat@gmail.com> | 2015-08-18 15:48:56 -0700 |
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committer | Anuj Phogat <anuj.phogat@gmail.com> | 2015-09-28 12:43:43 -0700 |
commit | 21fdc59d349eb396b48f0919dfd1a8dc234b96b1 (patch) | |
tree | 84fa0efee2db5fe3ea380e7e4ce2a1b7f6655259 /src/mesa/drivers/dri/i965/intel_mipmap_tree.c | |
parent | 5edd9961c15a80d557ba42f48c97a471b23d9c5e (diff) | |
download | external_mesa3d-21fdc59d349eb396b48f0919dfd1a8dc234b96b1.zip external_mesa3d-21fdc59d349eb396b48f0919dfd1a8dc234b96b1.tar.gz external_mesa3d-21fdc59d349eb396b48f0919dfd1a8dc234b96b1.tar.bz2 |
i965: Add a helper function intel_get_tile_dims()
V2:
- Do the tile width/height computations in the new helper
function and use it later in intel_miptree_get_tile_masks().
- Change the name to intel_get_tile_dims().
V3: Return the tile_h in number of rows in place of bytes.
Document the units of tile_w, tile_h parameters.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_mipmap_tree.c')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 82 |
1 files changed, 60 insertions, 22 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 2150708..ee5904d 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -557,35 +557,15 @@ static unsigned long intel_get_yf_ys_bo_size(struct intel_mipmap_tree *mt, unsigned *alignment, unsigned long *pitch) { - const uint32_t bpp = mt->cpp * 8; - const uint32_t aspect_ratio = (bpp == 16 || bpp == 64) ? 2 : 1; uint32_t tile_width, tile_height; unsigned long stride, size, aligned_y; assert(mt->tr_mode != INTEL_MIPTREE_TRMODE_NONE); - - switch (bpp) { - case 8: - tile_height = 64; - break; - case 16: - case 32: - tile_height = 32; - break; - case 64: - case 128: - tile_height = 16; - break; - default: - unreachable("not reached"); - } - - if (mt->tr_mode == INTEL_MIPTREE_TRMODE_YS) - tile_height *= 4; + intel_get_tile_dims(mt->tiling, mt->tr_mode, mt->cpp, + &tile_width, &tile_height); aligned_y = ALIGN(mt->total_height, tile_height); stride = mt->total_width * mt->cpp; - tile_width = tile_height * mt->cpp * aspect_ratio; stride = ALIGN(stride, tile_width); size = stride * aligned_y; @@ -1075,6 +1055,64 @@ intel_miptree_get_image_offset(const struct intel_mipmap_tree *mt, *y = mt->level[level].slice[slice].y_offset; } + +/** + * This function computes the tile_w (in bytes) and tile_h (in rows) of + * different tiling patterns. If the BO is untiled, tile_w is set to cpp + * and tile_h is set to 1. + */ +void +intel_get_tile_dims(uint32_t tiling, uint32_t tr_mode, uint32_t cpp, + uint32_t *tile_w, uint32_t *tile_h) +{ + if (tr_mode == INTEL_MIPTREE_TRMODE_NONE) { + switch (tiling) { + case I915_TILING_X: + *tile_w = 512; + *tile_h = 8; + break; + case I915_TILING_Y: + *tile_w = 128; + *tile_h = 32; + break; + case I915_TILING_NONE: + *tile_w = cpp; + *tile_h = 1; + break; + default: + unreachable("not reached"); + } + } else { + uint32_t aspect_ratio = 1; + assert(_mesa_is_pow_two(cpp)); + + switch (cpp) { + case 1: + *tile_h = 64; + break; + case 2: + case 4: + *tile_h = 32; + break; + case 8: + case 16: + *tile_h = 16; + break; + default: + unreachable("not reached"); + } + + if (cpp == 2 || cpp == 8) + aspect_ratio = 2; + + if (tr_mode == INTEL_MIPTREE_TRMODE_YS) + *tile_h *= 4; + + *tile_w = *tile_h * aspect_ratio * cpp; + } +} + + /** * This function computes masks that may be used to select the bits of the X * and Y coordinates that indicate the offset within a tile. If the BO is |