i965: Always use Y-tiled buffers on SKL+

Starting with Skylake, the display engine is capable of scanning out from
Y-tiled buffers. As such, we can and should use Y-tiling for better efficiency.
This also has the added benefit of being able to fast clear the winsys buffer.

Note that the buffer allocation done for mipmaps will already never allocate an
X-tiled buffer for GEN9.

This has an almost universal positive impact on benchmarks, some improving by as
much as 20%.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

1 files changed, 8 insertions, 2 deletions

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 26c297d..8099ea7 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -144,7 +144,8 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format,
  *   by half the block width, and Y coordinates by half the block height.
  */
 void
-intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt,
+intel_get_non_msrt_mcs_alignment(const struct brw_context *brw,
+                                 const struct intel_mipmap_tree *mt,
                                  unsigned *width_px, unsigned *height)
 {
    switch (mt->tiling) {
@@ -156,6 +157,11 @@ intel_get_non_msrt_mcs_alignment(const struct intel_mipmap_tree *mt,
       *height = 4;
       break;
    case I915_TILING_X:
+      /* The docs are somewhat confusing with the way the tables are displayed.
+       * However, it does clearly state: "MCS and Lossless compression is
+       * supported for TiledY/TileYs/TileYf non-MSRTs only."
+       */
+      assert(brw->gen < 9);
       *width_px = 64 / mt->cpp;
       *height = 2;
    }
@@ -1552,7 +1558,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
    const mesa_format format = MESA_FORMAT_R_UINT32;
    unsigned block_width_px;
    unsigned block_height;
-   intel_get_non_msrt_mcs_alignment(mt, &block_width_px, &block_height);
+   intel_get_non_msrt_mcs_alignment(brw, mt, &block_width_px, &block_height);
    unsigned width_divisor = block_width_px * 4;
    unsigned height_divisor = block_height * 8;