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| author | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-07-14 09:56:09 -0700 |
|---|---|---|
| committer | Ben Widawsky <benjamin.widawsky@intel.com> | 2015-07-16 17:02:35 -0700 |
| commit | 3a31876600cb5c4d90c998ecb5635c602eeb2bd1 (patch) | |
| tree | 0ef7a45ca9ba01f0eae221995e3c8cfd15f1b980 /src/mesa/drivers/dri/i965/intel_mipmap_tree.h | |
| parent | ef42352ff4e1feeea7338db73f540038c6755472 (diff) | |
| download | external_mesa3d-3a31876600cb5c4d90c998ecb5635c602eeb2bd1.zip external_mesa3d-3a31876600cb5c4d90c998ecb5635c602eeb2bd1.tar.gz external_mesa3d-3a31876600cb5c4d90c998ecb5635c602eeb2bd1.tar.bz2 | |
i965: Push miptree tiling request into flags
With the last few patches a way was provided to influence lower layer miptree
layout and allocation decisions via flags (replacing bools). For simplicity, I
chose not to touch the tiling requests because the change was slightly less
mechanical than replacing the bools.
The goal is to organize the code so we can continue to add new parameters and
tiling types while minimizing risk to the existing code, and not having to
constantly add new function parameters.
v2: Rebased on Anuj's recent Yf/Ys changes
Fix non-msrt MCS allocation (was only happening in gen8 case before)
v3: small fix in assertion requested by Chad
v4: Use parens to get the order right from v3.
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_mipmap_tree.h')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h index bde6daa..89fdccb 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h @@ -516,12 +516,6 @@ struct intel_mipmap_tree GLuint refcount; }; -enum intel_miptree_tiling_mode { - INTEL_MIPTREE_TILING_ANY, - INTEL_MIPTREE_TILING_Y, - INTEL_MIPTREE_TILING_NONE, -}; - void intel_get_non_msrt_mcs_alignment(struct brw_context *brw, struct intel_mipmap_tree *mt, @@ -541,8 +535,15 @@ enum { MIPTREE_LAYOUT_FOR_BO = 1 << 2, MIPTREE_LAYOUT_DISABLE_AUX = 1 << 3, MIPTREE_LAYOUT_FORCE_HALIGN16 = 1 << 4, + + MIPTREE_LAYOUT_ALLOC_YTILED = 1 << 5, + MIPTREE_LAYOUT_ALLOC_XTILED = 1 << 6, + MIPTREE_LAYOUT_ALLOC_LINEAR = 1 << 7, }; +#define MIPTREE_LAYOUT_ALLOC_ANY_TILED (MIPTREE_LAYOUT_ALLOC_YTILED | \ + MIPTREE_LAYOUT_ALLOC_XTILED) + struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw, GLenum target, mesa_format format, @@ -552,7 +553,6 @@ struct intel_mipmap_tree *intel_miptree_create(struct brw_context *brw, GLuint height0, GLuint depth0, GLuint num_samples, - enum intel_miptree_tiling_mode, uint32_t flags); struct intel_mipmap_tree * @@ -771,7 +771,6 @@ brw_miptree_get_vertical_slice_pitch(const struct brw_context *brw, void brw_miptree_layout(struct brw_context *brw, struct intel_mipmap_tree *mt, - enum intel_miptree_tiling_mode requested, uint32_t layout_flags); void *intel_miptree_map_raw(struct brw_context *brw, |