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| author | Jordan Justen <jordan.l.justen@intel.com> | 2014-05-28 09:05:37 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2014-08-15 20:11:41 -0700 |
| commit | 27f5fa7a3777332b2e60ccf10dc636ad84a3c478 (patch) | |
| tree | b916d200e7d2a53222bbddcee32b4d64720ca694 /src/mesa/drivers/dri/i965/intel_tex_image.c | |
| parent | 7e856d0b180d3fc0c25f94156ded4a539f456030 (diff) | |
| download | external_mesa3d-27f5fa7a3777332b2e60ccf10dc636ad84a3c478.zip external_mesa3d-27f5fa7a3777332b2e60ccf10dc636ad84a3c478.tar.gz external_mesa3d-27f5fa7a3777332b2e60ccf10dc636ad84a3c478.tar.bz2 | |
i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LOD
gen6 does not support multiple miplevels with separate
stencil/hiz. Therefore we need to layout its miptree with no mipmap
spacing between the slices of each miplevel.
v3:
* Use new array_layout enum
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src/mesa/drivers/dri/i965/intel_tex_image.c')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_tex_image.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c index 029d59b..3317779 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_image.c +++ b/src/mesa/drivers/dri/i965/intel_tex_image.c @@ -81,7 +81,8 @@ intel_miptree_create_for_teximage(struct brw_context *brw, depth, expect_accelerated_upload, intelImage->base.Base.NumSamples, - INTEL_MIPTREE_TILING_ANY); + INTEL_MIPTREE_TILING_ANY, + false); } /* XXX: Do this for TexSubImage also: |