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author | Kenneth Graunke <kenneth@whitecape.org> | 2014-12-22 00:55:37 -0800 |
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committer | Kenneth Graunke <kenneth@whitecape.org> | 2014-12-24 00:15:40 -0800 |
commit | b7f14e03e3de218aedf4ba9439384c7bcbc091eb (patch) | |
tree | 0819518c8e2b7a47855834cd00bb1193d7c9a3f1 /src/mesa/drivers/dri/i965 | |
parent | f332cf92b69e52de3cb7c3088ad1efd2e291bb88 (diff) | |
download | external_mesa3d-b7f14e03e3de218aedf4ba9439384c7bcbc091eb.zip external_mesa3d-b7f14e03e3de218aedf4ba9439384c7bcbc091eb.tar.gz external_mesa3d-b7f14e03e3de218aedf4ba9439384c7bcbc091eb.tar.bz2 |
i965: Cache register write capability checks.
Our ability to perform register writes depends on the hardware and
kernel version. It shouldn't ever change on a per-context basis,
so we only need to check once.
Checking introduces a synchronization point between the CPU and GPU:
even though we submit very few GPU commands, the GPU might be busy doing
other work, which could cause us to stall for a while.
On an idle i7 4750HQ, this improves performance in OglDrvCtx (a context
creation microbenchmark) by 6.14748% +/- 1.6837% (n=20). With Unigine
Valley running in the background (to keep the GPU busy), it improves
performance in OglDrvCtx by 2290.92% +/- 29.5274% (n=5).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Diffstat (limited to 'src/mesa/drivers/dri/i965')
-rw-r--r-- | src/mesa/drivers/dri/i965/intel_extensions.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index bbbb76f..3cbfaaf 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -46,6 +46,10 @@ can_do_pipelined_register_writes(struct brw_context *brw) if (brw->gen >= 8) return true; + static int result = -1; + if (result != -1) + return result; + /* We use SO_WRITE_OFFSET0 since you're supposed to write it (unlike the * statistics registers), and we already reset it to zero before using it. */ @@ -91,6 +95,8 @@ can_do_pipelined_register_writes(struct brw_context *brw) bool success = data[offset] == expected_value; drm_intel_bo_unmap(brw->batch.workaround_bo); + result = success; + return success; } @@ -100,6 +106,10 @@ can_write_oacontrol(struct brw_context *brw) if (brw->gen < 6 || brw->gen >= 8) return false; + static int result = -1; + if (result != -1) + return result; + /* Set "Select Context ID" to a particular address (which is likely not a * context), but leave all counting disabled. This should be harmless. */ @@ -150,6 +160,8 @@ can_write_oacontrol(struct brw_context *brw) bool success = data[offset] == expected_value; drm_intel_bo_unmap(brw->batch.workaround_bo); + result = success; + return success; } |