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| author | Eric Anholt <eric@anholt.net> | 2011-06-17 18:20:36 -0700 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2011-06-20 08:37:43 -0700 |
| commit | dfada714f8db3deea2fea3583c3c166a78db1117 (patch) | |
| tree | 7c192cb7f1a98c7c0fa081b8d602ec6969e5c209 /src/mesa/drivers/dri/intel/intel_batchbuffer.h | |
| parent | 8f9e8d79c8c180e4254d01c688969d6d45386891 (diff) | |
| download | external_mesa3d-dfada714f8db3deea2fea3583c3c166a78db1117.zip external_mesa3d-dfada714f8db3deea2fea3583c3c166a78db1117.tar.gz external_mesa3d-dfada714f8db3deea2fea3583c3c166a78db1117.tar.bz2 | |
i965/gen6: Use an BO instead of writing to address 0 for PIPE_CONTROL W/A.
This was spectacularly unsafe. On my system, address 0 happens to be
the hardware status page for the render ring, and the first quadword
of that happens to contain nothing we ever look at, but I sure didn't
look forward to having to debug some day when, for example, the kernel
happened to bind the ringbuffer before binding the hwsp.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_batchbuffer.h')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_batchbuffer.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h index a0a5c98..3ed88d0 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h @@ -9,6 +9,7 @@ #define BATCH_RESERVED 16 +void intel_batchbuffer_init(struct intel_context *intel); void intel_batchbuffer_reset(struct intel_context *intel); void intel_batchbuffer_free(struct intel_context *intel); |