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| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-12-23 15:06:33 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2010-12-23 17:29:46 +0800 |
| commit | 845d651cf686ba885dffd9e05df971fa68c3431a (patch) | |
| tree | 85a9921b9de3613afe17151f839a7dd1b7e04589 /src/mesa/drivers/dri/intel/intel_reg.h | |
| parent | 1e7bfcc70719054e6fb69fc5313edd0420715e2c (diff) | |
| download | external_mesa3d-845d651cf686ba885dffd9e05df971fa68c3431a.zip external_mesa3d-845d651cf686ba885dffd9e05df971fa68c3431a.tar.gz external_mesa3d-845d651cf686ba885dffd9e05df971fa68c3431a.tar.bz2 | |
i965: Use MI_FLUSH_DW for blt ring flush on sandybridge
Old MI_FLUSH command is deprecated on sandybridge blt.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_reg.h')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_reg.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h index 955b100..5258699 100644 --- a/src/mesa/drivers/dri/intel/intel_reg.h +++ b/src/mesa/drivers/dri/intel/intel_reg.h @@ -37,6 +37,8 @@ #define FLUSH_MAP_CACHE (1 << 0) #define INHIBIT_FLUSH_RENDER_CACHE (1 << 2) +#define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2) + /* Stalls command execution waiting for the given events to have occurred. */ #define MI_WAIT_FOR_EVENT (CMD_MI | (0x3 << 23)) #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) |