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| author | Eric Anholt <eric@anholt.net> | 2009-06-03 16:40:20 +0000 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-06-04 14:00:43 +0000 |
| commit | 1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e (patch) | |
| tree | 2cd5c5303ec85edfc47ab8f80e60a88134f461e0 /src/mesa/drivers/dri/intel/intel_tex_copy.c | |
| parent | 165ae5e2fb57bdb64b4cf01271b4effeb811f675 (diff) | |
| download | external_mesa3d-1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e.zip external_mesa3d-1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e.tar.gz external_mesa3d-1ba96651e12b3c74fb9c8f5a61b183ef36a27b1e.tar.bz2 | |
intel: Add support for tiled textures.
This is about a 30% performance win in OA with high settings on my GM45,
and experiments with 915GM indicate that it'll be around a 20% win there.
Currently, 915-class hardware is seriously hurt by the fact that we use
fence regs to control the tiling even for 3D instructions that could live
without them, so we spend a bunch of time waiting on previous rendering in
order to pull fences off. Thus, the texture_tiling driconf option defaults
off there for now.
Diffstat (limited to 'src/mesa/drivers/dri/intel/intel_tex_copy.c')
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_tex_copy.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index a25626a..673b8fa 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -118,8 +118,12 @@ do_copy_texsubimage(struct intel_context *intel, dstx += x - orig_x; dsty += y - orig_y; - /* image_offset may be non-page-aligned, but that's illegal for tiling. */ - assert(intelImage->mt->region->tiling == I915_TILING_NONE); + /* Can't blit to tiled buffers with non-tile-aligned offset. */ + if (intelImage->mt->region->tiling != I915_TILING_NONE && + (image_offset & 4095) != 0) { + UNLOCK_HARDWARE(intel); + return GL_FALSE; + } if (ctx->ReadBuffer->Name == 0) { /* reading from a window, adjust x, y */ |