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authorRoland Scheidegger <rscheidegger@gmx.ch>2005-08-31 19:11:09 +0000
committerRoland Scheidegger <rscheidegger@gmx.ch>2005-08-31 19:11:09 +0000
commit36603539ccdb1c507724d8a1c314e6c9cc9863d9 (patch)
tree4d13da48ad1885057dc76d31f2bf63528f945d24 /src/mesa/drivers/dri/r200/r200_reg.h
parentd5783737f1b7ce30d724b70566efbf52394b7759 (diff)
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enable GL_ARB_texture_env_crossbar on r200, separate the enable bits for texture sampling and texture environment, optimize away texture sampling for units if the result is not used, always emit the env instructions in-order and try to eliminate GL_REPLACE env instructions.
Diffstat (limited to 'src/mesa/drivers/dri/r200/r200_reg.h')
-rw-r--r--src/mesa/drivers/dri/r200/r200_reg.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_reg.h b/src/mesa/drivers/dri/r200/r200_reg.h
index dd5f17c..d19f9df 100644
--- a/src/mesa/drivers/dri/r200/r200_reg.h
+++ b/src/mesa/drivers/dri/r200/r200_reg.h
@@ -172,6 +172,8 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R200_TEX_BLEND_4_ENABLE 0x00010000
#define R200_TEX_BLEND_5_ENABLE 0x00020000
#define R200_TEX_BLEND_6_ENABLE 0x00040000
+#define R200_TEX_BLEND_ENABLE_MASK 0x0007f800
+#define R200_TEX_BLEND_0_ENABLE_SHIFT (12)
#define R200_MULTI_PASS_ENABLE 0x00080000
#define R200_SPECULAR_ENABLE 0x00200000
#define R200_FOG_ENABLE 0x00400000
@@ -1146,6 +1148,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R200_TXC_CLAMP_WRAP (0 << 12)
#define R200_TXC_CLAMP_0_1 (1 << 12)
#define R200_TXC_CLAMP_8_8 (2 << 12)
+#define R200_TXC_OUTPUT_REG_SHIFT 16
#define R200_TXC_OUTPUT_REG_MASK (7 << 16)
#define R200_TXC_OUTPUT_REG_NONE (0 << 16)
#define R200_TXC_OUTPUT_REG_R0 (1 << 16)
@@ -1288,6 +1291,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define R200_TXA_CLAMP_WRAP (0 << 12)
#define R200_TXA_CLAMP_0_1 (1 << 12)
#define R200_TXA_CLAMP_8_8 (2 << 12)
+#define R200_TXA_OUTPUT_REG_SHIFT 16
#define R200_TXA_OUTPUT_REG_MASK (7 << 16)
#define R200_TXA_OUTPUT_REG_NONE (0 << 16)
#define R200_TXA_OUTPUT_REG_R0 (1 << 16)