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author | Jerome Glisse <glisse@freedesktop.org> | 2009-05-20 13:21:24 +0200 |
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committer | Jerome Glisse <glisse@freedesktop.org> | 2009-05-20 13:21:24 +0200 |
commit | 8308bf9ee155b405ad42e6621daf33a108330418 (patch) | |
tree | 09fadf1f5730ec4627febc5416ca2de3968534c1 /src/mesa/drivers/dri/r200/r200_state_init.c | |
parent | d039cf4574893e480d33f286e3526c6805d919fd (diff) | |
download | external_mesa3d-8308bf9ee155b405ad42e6621daf33a108330418.zip external_mesa3d-8308bf9ee155b405ad42e6621daf33a108330418.tar.gz external_mesa3d-8308bf9ee155b405ad42e6621daf33a108330418.tar.bz2 |
r200: fix indexed draw color order and cs missmatch
Diffstat (limited to 'src/mesa/drivers/dri/r200/r200_state_init.c')
-rw-r--r-- | src/mesa/drivers/dri/r200/r200_state_init.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c b/src/mesa/drivers/dri/r200/r200_state_init.c index be57ac3..a716779 100644 --- a/src/mesa/drivers/dri/r200/r200_state_init.c +++ b/src/mesa/drivers/dri/r200/r200_state_init.c @@ -295,12 +295,16 @@ VP_CHECK( tcl_vpp_size, ctx->VertexProgram.Current->Base.NumNativeParameters > 9 h.i = hdr; \ _start = h.veclinear.addr_lo | (h.veclinear.addr_hi << 8); \ _sz = h.veclinear.count * 4; \ + if (r200->radeon.radeonScreen->kernel_mm && _sz) { \ + BEGIN_BATCH_NO_AUTOSTATE(dwords); \ OUT_BATCH(CP_PACKET0(RADEON_SE_TCL_STATE_FLUSH, 0)); \ OUT_BATCH(0); \ OUT_BATCH(CP_PACKET0(R200_SE_TCL_VECTOR_INDX_REG, 0)); \ OUT_BATCH(_start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); \ OUT_BATCH(CP_PACKET0_ONE(R200_SE_TCL_VECTOR_DATA_REG, _sz - 1)); \ OUT_BATCH_TABLE((data), _sz); \ + END_BATCH(); \ + } \ } while(0) #define OUT_SCL(hdr, data) do { \ @@ -367,9 +371,7 @@ static void veclinear_emit(GLcontext *ctx, struct radeon_state_atom *atom) uint32_t dwords = atom->cmd_size; dwords += 4; - BEGIN_BATCH_NO_AUTOSTATE(dwords); OUT_VECLINEAR(atom->cmd[0], atom->cmd+1); - END_BATCH(); } static void scl_emit(GLcontext *ctx, struct radeon_state_atom *atom) |