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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-12-10 09:13:59 -0500 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-01-28 21:03:47 +0000 |
| commit | 2397a721291457c146c7f4bcd48adcb3b2d979bd (patch) | |
| tree | 016628c1fb29de41f0bbca307fa26eac43ae60dd /src/mesa/drivers/dri/radeon/radeon_span.h | |
| parent | 5dcd97f25c217450c9e3e0441246187219a01eca (diff) | |
| download | external_mesa3d-2397a721291457c146c7f4bcd48adcb3b2d979bd.zip external_mesa3d-2397a721291457c146c7f4bcd48adcb3b2d979bd.tar.gz external_mesa3d-2397a721291457c146c7f4bcd48adcb3b2d979bd.tar.bz2 | |
radeonsi: Enable VGPR spilling for all shader types v5
v2:
- Only emit write SPI_TMPRING_SIZE once per packet.
- Use context global scratch buffer.
v3:
- Patch shaders using WRITE_DATA packet instead of map/unmap.
- Emit ICACHE_FLUSH, CS_PARTIAL_FLUSH, PS_PARTIAL_FLUSH, and
VS_PARTIAL_FLUSH when patching shaders.
v4:
- Code cleanups.
- Remove unnecessary multiplies.
v5:
- Patch shaders in system memory and re-upload to vram.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Diffstat (limited to 'src/mesa/drivers/dri/radeon/radeon_span.h')
0 files changed, 0 insertions, 0 deletions