i965: Update STATE_BASE_ADDRESS for Broadwell.

v2: Fix missing "change" bit on instruction state base address
    (caught by Haihao Xiang).

v3: Add a perf_debug for missing MOCS setup, requested by Eric.

v4: Fix buffer sizes.  The value, specified at bit 12 and up, is
    actually measured in 4k pages.  We need to round up to the
    next multiple of 4k.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v3]
Reviewed-by: Matt Turner <mattst88@gmail.com> [v4]

4 files changed, 76 insertions, 1 deletions

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index 7092cc9..57afc9a 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -146,6 +146,7 @@ i965_FILES = \
 	gen8_fs_generator.cpp \
 	gen8_generator.cpp \
 	gen8_instruction.c \
+	gen8_misc_state.c \
 	gen8_sf_state.c \
 	gen8_vec4_generator.cpp \
 	gen8_vs_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 3947904..619f4c8 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -139,6 +139,7 @@ extern const struct brw_tracked_state gen8_wm_state;
 extern const struct brw_tracked_state gen8_raster_state;
 extern const struct brw_tracked_state gen8_sbe_state;
 extern const struct brw_tracked_state gen8_sf_state;
+extern const struct brw_tracked_state gen8_state_base_address;
 extern const struct brw_tracked_state gen8_vs_state;
 
 /* brw_misc_state.c */
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 86741a6..e4f8104 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -258,7 +258,7 @@ static const struct brw_tracked_state *gen8_atoms[] =
    &brw_wm_prog,
 
    /* Command packets: */
-   &brw_state_base_address,
+   &gen8_state_base_address,
 
    &brw_cc_vp,
    &gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c
new file mode 100644
index 0000000..ddc65a8
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "intel_batchbuffer.h"
+#include "brw_context.h"
+#include "brw_state.h"
+#include "brw_defines.h"
+
+/**
+ * Define the base addresses which some state is referenced from.
+ */
+static void upload_state_base_address(struct brw_context *brw)
+{
+   perf_debug("Missing MOCS setup for STATE_BASE_ADDRESS.");
+
+   BEGIN_BATCH(16);
+   OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (16 - 2));
+   /* General state base address: stateless DP read/write requests */
+   OUT_BATCH(1);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   /* Surface state base address: */
+   OUT_RELOC64(brw->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
+   /* Dynamic state base address: */
+   OUT_RELOC64(brw->batch.bo,
+               I915_GEM_DOMAIN_RENDER | I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+   /* Indirect object base address: MEDIA_OBJECT data */
+   OUT_BATCH(1);
+   OUT_BATCH(0);
+   /* Instruction base address: shader kernels (incl. SIP) */
+   OUT_RELOC64(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1);
+
+   /* General state buffer size */
+   OUT_BATCH(0xfffff001);
+   /* Dynamic state buffer size */
+   OUT_BATCH(ALIGN(brw->batch.bo->size, 4096) | 1);
+   /* Indirect object upper bound */
+   OUT_BATCH(0xfffff001);
+   /* Instruction access upper bound */
+   OUT_BATCH(ALIGN(brw->cache.bo->size, 4096) | 1);
+   ADVANCE_BATCH();
+
+   brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS;
+}
+
+const struct brw_tracked_state gen8_state_base_address = {
+   .dirty = {
+      .mesa = 0,
+      .brw = BRW_NEW_BATCH | BRW_NEW_PROGRAM_CACHE,
+      .cache = 0,
+   },
+   .emit = upload_state_base_address
+};