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| author | Jordan Justen <jordan.l.justen@intel.com> | 2013-04-19 01:00:20 -0700 |
|---|---|---|
| committer | Jordan Justen <jordan.l.justen@intel.com> | 2013-06-02 20:38:37 -0700 |
| commit | 6a5469cff9eb8167a9cf977b42bdcf423e400bb7 (patch) | |
| tree | 60f2b96cfe6f37fed92b95e92543bb8838b30ae9 /src/mesa/drivers/dri | |
| parent | 8312caf6737d51df6048397befa49cae10b5604d (diff) | |
| download | external_mesa3d-6a5469cff9eb8167a9cf977b42bdcf423e400bb7.zip external_mesa3d-6a5469cff9eb8167a9cf977b42bdcf423e400bb7.tar.gz external_mesa3d-6a5469cff9eb8167a9cf977b42bdcf423e400bb7.tar.bz2 | |
intel: add layered parameter to update_renderbuffer_surface
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src/mesa/drivers/dri')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 6 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.h | 1 |
3 files changed, 9 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index f73ea20..4d4d300 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -1315,6 +1315,7 @@ brw_update_null_renderbuffer_surface(struct brw_context *brw, unsigned int unit) static void brw_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, + bool layered, unsigned int unit) { struct intel_context *intel = &brw->intel; @@ -1328,6 +1329,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, /* _NEW_BUFFERS */ gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); + assert(!layered); + if (rb->TexImage && !brw->has_surface_tile_offset) { intel_renderbuffer_get_tile_offsets(irb, &tile_x, &tile_y); @@ -1424,7 +1427,8 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw) if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) { for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) { - intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], i); + intel->vtbl.update_renderbuffer_surface(brw, ctx->DrawBuffer->_ColorDrawBuffers[i], + ctx->DrawBuffer->Layered, i); } else { intel->vtbl.update_null_renderbuffer_surface(brw, i); } diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 0376705..0768438 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -523,6 +523,7 @@ gen7_update_null_renderbuffer_surface(struct brw_context *brw, unsigned unit) static void gen7_update_renderbuffer_surface(struct brw_context *brw, struct gl_renderbuffer *rb, + bool layered, unsigned int unit) { struct intel_context *intel = &brw->intel; @@ -534,6 +535,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, /* _NEW_BUFFERS */ gl_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); + assert(!layered); + uint32_t *surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 8 * 4, 32, &brw->wm.surf_offset[unit]); memset(surf, 0, 8 * 4); diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index c0f07ff..5420e76 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -196,6 +196,7 @@ struct intel_context unsigned surf_index); void (*update_renderbuffer_surface)(struct brw_context *brw, struct gl_renderbuffer *rb, + bool layered, unsigned unit); void (*update_null_renderbuffer_surface)(struct brw_context *brw, unsigned unit); |