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authorJason Ekstrand <jason.ekstrand@intel.com>2015-10-09 18:07:23 -0700
committerKenneth Graunke <kenneth@whitecape.org>2016-04-26 19:55:04 -0700
commitc7a09c057162ed0b7e9e039470c76bb79518876c (patch)
tree6dd95200538e03e5fe96b2afd80fe50f994527f7 /src/mesa/drivers/dri
parent30b37e4e9b619ddec258c602223f7c6af98062d9 (diff)
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i965/fs: Properly report regs_written from SAMPLEINFO
The previous behavior would only allocate one register and then write four thus potentially stomping three innocent bystanders. Cc: mesa-stable@lists.freedesktop.org Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Diffstat (limited to 'src/mesa/drivers/dri')
-rw-r--r--src/mesa/drivers/dri/i965/brw_fs_nir.cpp8
-rw-r--r--src/mesa/drivers/dri/i965/brw_shader.cpp3
2 files changed, 9 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 725f5da..43d3745 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -3205,12 +3205,18 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
case nir_texop_txs: op = ir_txs; break;
case nir_texop_texture_samples: {
fs_reg dst = retype(get_nir_dest(instr->dest), BRW_REGISTER_TYPE_D);
- fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, dst,
+
+ fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_D, 4);
+ fs_inst *inst = bld.emit(SHADER_OPCODE_SAMPLEINFO, tmp,
bld.vgrf(BRW_REGISTER_TYPE_D, 1),
texture_reg, texture_reg);
inst->mlen = 1;
inst->header_size = 1;
inst->base_mrf = -1;
+ inst->regs_written = 4 * (dispatch_width / 8);
+
+ /* Pick off the one component we care about */
+ bld.MOV(dst, tmp);
return;
}
case nir_texop_samples_identical: op = ir_samples_identical; break;
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index d9e654c..80fddfc 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -757,7 +757,8 @@ backend_instruction::is_tex() const
opcode == SHADER_OPCODE_TXS ||
opcode == SHADER_OPCODE_LOD ||
opcode == SHADER_OPCODE_TG4 ||
- opcode == SHADER_OPCODE_TG4_OFFSET);
+ opcode == SHADER_OPCODE_TG4_OFFSET ||
+ opcode == SHADER_OPCODE_SAMPLEINFO);
}
bool