diff options
author | Alan Hourihane <alanh@tungstengraphics.com> | 2008-12-08 14:29:50 +0000 |
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committer | Alan Hourihane <alanh@tungstengraphics.com> | 2008-12-08 14:29:50 +0000 |
commit | 33a1f495d4bb19288680b9812c6ec1235302d215 (patch) | |
tree | d47067fe24d530c660b75ee80cdcec72f10d9ed0 /src/mesa/drivers | |
parent | bcd5dda4358a5e47551278477bd00d2c63415c44 (diff) | |
parent | bdc8ac4426f00eaafbe8ca0d356563efe390294d (diff) | |
download | external_mesa3d-33a1f495d4bb19288680b9812c6ec1235302d215.zip external_mesa3d-33a1f495d4bb19288680b9812c6ec1235302d215.tar.gz external_mesa3d-33a1f495d4bb19288680b9812c6ec1235302d215.tar.bz2 |
Merge commit 'origin/master' into gallium-0.2
Conflicts:
progs/glsl/Makefile
Diffstat (limited to 'src/mesa/drivers')
-rw-r--r-- | src/mesa/drivers/dri/i915/intel_render.c | 25 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i915/intel_tris.c | 98 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 12 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_curbe.c | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_draw.c | 103 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_program.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 125 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_vtbl.c | 2 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm.c | 6 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm.h | 3 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_fp.c | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_iz.c | 64 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_state.c | 7 | ||||
-rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_context.h | 1 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_reg.h | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_screen.c | 1 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_screen.h | 1 | ||||
-rw-r--r-- | src/mesa/drivers/dri/intel/intel_tex_copy.c | 4 |
19 files changed, 320 insertions, 151 deletions
diff --git a/src/mesa/drivers/dri/i915/intel_render.c b/src/mesa/drivers/dri/i915/intel_render.c index 467abe4..410052b 100644 --- a/src/mesa/drivers/dri/i915/intel_render.c +++ b/src/mesa/drivers/dri/i915/intel_render.c @@ -117,6 +117,26 @@ intelDmaPrimitive(struct intel_context *intel, GLenum prim) intel_set_prim(intel, hw_prim[prim]); } +static inline GLuint intel_get_vb_max(struct intel_context *intel) +{ + GLuint ret; + + if (intel->intelScreen->no_vbo) + ret = intel->batch->size - 1500; + else + ret = INTEL_VB_SIZE; + ret /= (intel->vertex_size * 4); + return ret; +} + +static inline GLuint intel_get_current_max(struct intel_context *intel) +{ + + if (intel->intelScreen->no_vbo) + return intel_get_vb_max(intel); + else + return (INTEL_VB_SIZE - intel->prim.current_offset) / (intel->vertex_size * 4); +} #define LOCAL_VARS struct intel_context *intel = intel_context(ctx) #define INIT( prim ) \ @@ -126,9 +146,8 @@ do { \ #define FLUSH() INTEL_FIREVERTICES(intel) -#define GET_SUBSEQUENT_VB_MAX_VERTS() (INTEL_VB_SIZE / (intel->vertex_size * 4)) -#define GET_CURRENT_VB_MAX_VERTS() \ - ((INTEL_VB_SIZE - intel->prim.current_offset) / (intel->vertex_size * 4)) +#define GET_SUBSEQUENT_VB_MAX_VERTS() intel_get_vb_max(intel) +#define GET_CURRENT_VB_MAX_VERTS() intel_get_current_max(intel) #define ALLOC_VERTS(nr) intel_get_prim_space(intel, nr) diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c index 797d6c5..c4708dc 100644 --- a/src/mesa/drivers/dri/i915/intel_tris.c +++ b/src/mesa/drivers/dri/i915/intel_tris.c @@ -61,9 +61,101 @@ static void intelRenderPrimitive(GLcontext * ctx, GLenum prim); static void intelRasterPrimitive(GLcontext * ctx, GLenum rprim, GLuint hwprim); +static void +intel_flush_inline_primitive(struct intel_context *intel) +{ + GLuint used = intel->batch->ptr - intel->prim.start_ptr; + + assert(intel->prim.primitive != ~0); + +/* _mesa_printf("/\n"); */ + + if (used < 8) + goto do_discard; + + *(int *) intel->prim.start_ptr = (_3DPRIMITIVE | + intel->prim.primitive | (used / 4 - 2)); + + goto finished; + + do_discard: + intel->batch->ptr -= used; + + finished: + intel->prim.primitive = ~0; + intel->prim.start_ptr = 0; + intel->prim.flush = 0; +} + +static void intel_start_inline(struct intel_context *intel, uint32_t prim) +{ + BATCH_LOCALS; + uint32_t batch_flags = LOOP_CLIPRECTS; + + intel_wait_flips(intel); + intel->vtbl.emit_state(intel); + + intel->no_batch_wrap = GL_TRUE; + + /*_mesa_printf("%s *", __progname);*/ + + /* Emit a slot which will be filled with the inline primitive + * command later. + */ + BEGIN_BATCH(2, batch_flags); + OUT_BATCH(0); + + assert((intel->batch->dirty_state & (1<<1)) == 0); + + intel->prim.start_ptr = intel->batch->ptr; + intel->prim.primitive = prim; + intel->prim.flush = intel_flush_inline_primitive; + + OUT_BATCH(0); + ADVANCE_BATCH(); + + intel->no_batch_wrap = GL_FALSE; +/* _mesa_printf(">"); */ +} + +static void intel_wrap_inline(struct intel_context *intel) +{ + GLuint prim = intel->prim.primitive; + + intel_flush_inline_primitive(intel); + intel_batchbuffer_flush(intel->batch); + intel_start_inline(intel, prim); /* ??? */ +} + +static GLuint *intel_extend_inline(struct intel_context *intel, GLuint dwords) +{ + GLuint sz = dwords * sizeof(GLuint); + GLuint *ptr; + + assert(intel->prim.flush == intel_flush_inline_primitive); + + if (intel_batchbuffer_space(intel->batch) < sz) + intel_wrap_inline(intel); + +/* _mesa_printf("."); */ + + intel->vtbl.assert_not_dirty(intel); + + ptr = (GLuint *) intel->batch->ptr; + intel->batch->ptr += sz; + + return ptr; +} + /** Sets the primitive type for a primitive sequence, flushing as needed. */ void intel_set_prim(struct intel_context *intel, uint32_t prim) { + /* if we have no VBOs */ + + if (intel->intelScreen->no_vbo) { + intel_start_inline(intel, prim); + return; + } if (prim != intel->prim.primitive) { INTEL_FIREVERTICES(intel); intel->prim.primitive = prim; @@ -75,6 +167,10 @@ uint32_t *intel_get_prim_space(struct intel_context *intel, unsigned int count) { uint32_t *addr; + if (intel->intelScreen->no_vbo) { + return intel_extend_inline(intel, count * intel->vertex_size); + } + /* Check for space in the existing VB */ if (intel->prim.vb_bo == NULL || (intel->prim.current_offset + @@ -155,7 +251,7 @@ void intel_flush_prim(struct intel_context *intel) #if 0 printf("emitting %d..%d=%d vertices size %d\n", offset, - intel->prim.current_offset, intel->prim.count, + intel->prim.current_offset, count, intel->vertex_size * 4); #endif diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index e3904be..7798010 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -133,16 +133,16 @@ struct brw_context; #define BRW_NEW_PSP 0x800 #define BRW_NEW_METAOPS 0x1000 #define BRW_NEW_FENCE 0x2000 -#define BRW_NEW_LOCK 0x4000 -#define BRW_NEW_INDICES 0x8000 -#define BRW_NEW_VERTICES 0x10000 +#define BRW_NEW_INDICES 0x4000 +#define BRW_NEW_VERTICES 0x8000 /** * Used for any batch entry with a relocated pointer that will be used * by any 3D rendering. */ -#define BRW_NEW_BATCH 0x8000 +#define BRW_NEW_BATCH 0x10000 /** brw->depth_region updated */ -#define BRW_NEW_DEPTH_BUFFER 0x10000 +#define BRW_NEW_DEPTH_BUFFER 0x20000 +#define BRW_NEW_NR_SURFACES 0x40000 struct brw_state_flags { /** State update flags signalled by mesa internals */ @@ -158,7 +158,6 @@ struct brw_state_flags { struct brw_vertex_program { struct gl_vertex_program program; GLuint id; - GLuint param_state; /* flags indicating state tracked by params */ }; @@ -166,7 +165,6 @@ struct brw_vertex_program { struct brw_fragment_program { struct gl_fragment_program program; GLuint id; - GLuint param_state; /* flags indicating state tracked by params */ }; diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c index c7bac7b..fbf473a 100644 --- a/src/mesa/drivers/dri/i965/brw_curbe.c +++ b/src/mesa/drivers/dri/i965/brw_curbe.c @@ -184,8 +184,8 @@ static void prepare_constant_buffer(struct brw_context *brw) * function will also be called whenever fp or vp changes. */ brw->curbe.tracked_state.dirty.mesa = (_NEW_TRANSFORM|_NEW_PROJECTION); - brw->curbe.tracked_state.dirty.mesa |= vp->param_state; - brw->curbe.tracked_state.dirty.mesa |= fp->param_state; + brw->curbe.tracked_state.dirty.mesa |= vp->program.Base.Parameters->StateFlags; + brw->curbe.tracked_state.dirty.mesa |= fp->program.Base.Parameters->StateFlags; if (sz == 0) { diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c index f893dd6..c3a26fc 100644 --- a/src/mesa/drivers/dri/i965/brw_draw.c +++ b/src/mesa/drivers/dri/i965/brw_draw.c @@ -49,7 +49,7 @@ #define FILE_DEBUG_FLAG DEBUG_BATCH -static GLuint hw_prim[GL_POLYGON+1] = { +static GLuint prim_to_hw_prim[GL_POLYGON+1] = { _3DPRIM_POINTLIST, _3DPRIM_LINELIST, _3DPRIM_LINELOOP, @@ -103,12 +103,9 @@ static GLuint brw_set_prim(struct brw_context *brw, GLenum prim) brw->intel.reduced_primitive = reduced_prim[prim]; brw->state.dirty.brw |= BRW_NEW_REDUCED_PRIMITIVE; } - - brw_validate_state(brw); - brw_upload_state(brw); } - return hw_prim[prim]; + return prim_to_hw_prim[prim]; } @@ -123,9 +120,9 @@ static GLuint trim(GLenum prim, GLuint length) } -static void brw_emit_prim( struct brw_context *brw, - const struct _mesa_prim *prim ) - +static void brw_emit_prim(struct brw_context *brw, + const struct _mesa_prim *prim, + uint32_t hw_prim) { struct brw_3d_primitive prim_packet; @@ -136,7 +133,7 @@ static void brw_emit_prim( struct brw_context *brw, prim_packet.header.opcode = CMD_3D_PRIM; prim_packet.header.length = sizeof(prim_packet)/4 - 2; prim_packet.header.pad = 0; - prim_packet.header.topology = brw_set_prim(brw, prim->mode); + prim_packet.header.topology = hw_prim; prim_packet.header.indexed = prim->indexed; prim_packet.verts_per_instance = trim(prim->mode, prim->count); @@ -258,11 +255,15 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, struct brw_context *brw = brw_context(ctx); GLboolean retval = GL_FALSE; GLboolean warn = GL_FALSE; + GLboolean first_time = GL_TRUE; GLuint i; if (ctx->NewState) _mesa_update_state( ctx ); + if (check_fallbacks(brw, prim, nr_prims)) + return GL_FALSE; + brw_validate_textures( brw ); /* Bind all inputs, derive varying and size information: @@ -275,6 +276,7 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, brw->vb.min_index = min_index; brw->vb.max_index = max_index; brw->state.dirty.brw |= BRW_NEW_VERTICES; + /* Have to validate state quite late. Will rebuild tnl_program, * which depends on varying information. * @@ -289,59 +291,58 @@ static GLboolean brw_try_draw_prims( GLcontext *ctx, return GL_TRUE; } - /* Flush the batch if it's approaching full, so that we don't wrap while - * we've got validated state that needs to be in the same batch as the - * primitives. This fraction is just a guess (minimal full state plus - * a primitive is around 512 bytes), and would be better if we had - * an upper bound of how much we might emit in a single - * brw_try_draw_prims(). - */ - intel_batchbuffer_require_space(intel->batch, intel->batch->size / 4, - LOOP_CLIPRECTS); - { - /* Set the first primitive early, ahead of validate_state: + for (i = 0; i < nr_prims; i++) { + uint32_t hw_prim; + + /* Flush the batch if it's approaching full, so that we don't wrap while + * we've got validated state that needs to be in the same batch as the + * primitives. This fraction is just a guess (minimal full state plus + * a primitive is around 512 bytes), and would be better if we had + * an upper bound of how much we might emit in a single + * brw_try_draw_prims(). */ - brw_set_prim(brw, prim[0].mode); + intel_batchbuffer_require_space(intel->batch, intel->batch->size / 4, + LOOP_CLIPRECTS); - brw_validate_state( brw ); + hw_prim = brw_set_prim(brw, prim[i].mode); - /* Various fallback checks: - */ - if (brw->intel.Fallback) - goto out; + if (first_time || (brw->state.dirty.brw & BRW_NEW_PRIMITIVE)) { + first_time = GL_FALSE; - if (check_fallbacks( brw, prim, nr_prims )) - goto out; + /* Various fallback checks: */ + if (brw->intel.Fallback) + goto out; - /* Check that we can fit our state in with our existing batchbuffer, or - * flush otherwise. - */ - if (dri_bufmgr_check_aperture_space(brw->state.validated_bos, - brw->state.validated_bo_count)) { - static GLboolean warned; - intel_batchbuffer_flush(intel->batch); - - /* Validate the state after we flushed the batch (which would have - * changed the set of dirty state). If we still fail to - * check_aperture, warn of what's happening, but attempt to continue - * on since it may succeed anyway, and the user would probably rather - * see a failure and a warning than a fallback. - */ brw_validate_state(brw); - if (!warned && - dri_bufmgr_check_aperture_space(brw->state.validated_bos, + + /* Check that we can fit our state in with our existing batchbuffer, or + * flush otherwise. + */ + if (dri_bufmgr_check_aperture_space(brw->state.validated_bos, brw->state.validated_bo_count)) { - warn = GL_TRUE; - warned = GL_TRUE; + static GLboolean warned; + intel_batchbuffer_flush(intel->batch); + + /* Validate the state after we flushed the batch (which would have + * changed the set of dirty state). If we still fail to + * check_aperture, warn of what's happening, but attempt to continue + * on since it may succeed anyway, and the user would probably rather + * see a failure and a warning than a fallback. + */ + brw_validate_state(brw); + if (!warned && + dri_bufmgr_check_aperture_space(brw->state.validated_bos, + brw->state.validated_bo_count)) { + warn = GL_TRUE; + warned = GL_TRUE; + } } - } - - brw_upload_state(brw); - for (i = 0; i < nr_prims; i++) { - brw_emit_prim(brw, &prim[i]); + brw_upload_state(brw); } + brw_emit_prim(brw, &prim[i], hw_prim); + retval = GL_TRUE; } diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index c38610b..a18dee8 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -117,7 +117,6 @@ static void brwProgramStringNotify( GLcontext *ctx, if (p == fp) brw->state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM; p->id = brw->program_id++; - p->param_state = p->program.Base.Parameters->StateFlags; } else if (target == GL_VERTEX_PROGRAM_ARB) { struct brw_context *brw = brw_context(ctx); @@ -129,7 +128,6 @@ static void brwProgramStringNotify( GLcontext *ctx, _mesa_insert_mvp_code(ctx, &p->program); } p->id = brw->program_id++; - p->param_state = p->program.Base.Parameters->StateFlags; /* Also tell tnl about it: */ diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 7a642bd..5124535 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -181,6 +181,118 @@ brw_clear_validated_bos(struct brw_context *brw) brw->state.validated_bo_count = 0; } +struct dirty_bit_map { + uint32_t bit; + char *name; + uint32_t count; +}; + +#define DEFINE_BIT(name) {name, #name, 0} + +static struct dirty_bit_map mesa_bits[] = { + DEFINE_BIT(_NEW_MODELVIEW), + DEFINE_BIT(_NEW_PROJECTION), + DEFINE_BIT(_NEW_TEXTURE_MATRIX), + DEFINE_BIT(_NEW_COLOR_MATRIX), + DEFINE_BIT(_NEW_ACCUM), + DEFINE_BIT(_NEW_COLOR), + DEFINE_BIT(_NEW_DEPTH), + DEFINE_BIT(_NEW_EVAL), + DEFINE_BIT(_NEW_FOG), + DEFINE_BIT(_NEW_HINT), + DEFINE_BIT(_NEW_LIGHT), + DEFINE_BIT(_NEW_LINE), + DEFINE_BIT(_NEW_PIXEL), + DEFINE_BIT(_NEW_POINT), + DEFINE_BIT(_NEW_POLYGON), + DEFINE_BIT(_NEW_POLYGONSTIPPLE), + DEFINE_BIT(_NEW_SCISSOR), + DEFINE_BIT(_NEW_STENCIL), + DEFINE_BIT(_NEW_TEXTURE), + DEFINE_BIT(_NEW_TRANSFORM), + DEFINE_BIT(_NEW_VIEWPORT), + DEFINE_BIT(_NEW_PACKUNPACK), + DEFINE_BIT(_NEW_ARRAY), + DEFINE_BIT(_NEW_RENDERMODE), + DEFINE_BIT(_NEW_BUFFERS), + DEFINE_BIT(_NEW_MULTISAMPLE), + DEFINE_BIT(_NEW_TRACK_MATRIX), + DEFINE_BIT(_NEW_PROGRAM), + {0, 0, 0} +}; + +static struct dirty_bit_map brw_bits[] = { + DEFINE_BIT(BRW_NEW_URB_FENCE), + DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM), + DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM), + DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS), + DEFINE_BIT(BRW_NEW_CURBE_OFFSETS), + DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE), + DEFINE_BIT(BRW_NEW_PRIMITIVE), + DEFINE_BIT(BRW_NEW_CONTEXT), + DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS), + DEFINE_BIT(BRW_NEW_INPUT_VARYING), + DEFINE_BIT(BRW_NEW_PSP), + DEFINE_BIT(BRW_NEW_METAOPS), + DEFINE_BIT(BRW_NEW_FENCE), + DEFINE_BIT(BRW_NEW_INDICES), + DEFINE_BIT(BRW_NEW_VERTICES), + DEFINE_BIT(BRW_NEW_BATCH), + DEFINE_BIT(BRW_NEW_DEPTH_BUFFER), + {0, 0, 0} +}; + +static struct dirty_bit_map cache_bits[] = { + DEFINE_BIT(CACHE_NEW_CC_VP), + DEFINE_BIT(CACHE_NEW_CC_UNIT), + DEFINE_BIT(CACHE_NEW_WM_PROG), + DEFINE_BIT(CACHE_NEW_SAMPLER_DEFAULT_COLOR), + DEFINE_BIT(CACHE_NEW_SAMPLER), + DEFINE_BIT(CACHE_NEW_WM_UNIT), + DEFINE_BIT(CACHE_NEW_SF_PROG), + DEFINE_BIT(CACHE_NEW_SF_VP), + DEFINE_BIT(CACHE_NEW_SF_UNIT), + DEFINE_BIT(CACHE_NEW_VS_UNIT), + DEFINE_BIT(CACHE_NEW_VS_PROG), + DEFINE_BIT(CACHE_NEW_GS_UNIT), + DEFINE_BIT(CACHE_NEW_GS_PROG), + DEFINE_BIT(CACHE_NEW_CLIP_VP), + DEFINE_BIT(CACHE_NEW_CLIP_UNIT), + DEFINE_BIT(CACHE_NEW_CLIP_PROG), + DEFINE_BIT(CACHE_NEW_SURFACE), + DEFINE_BIT(CACHE_NEW_SURF_BIND), + {0, 0, 0} +}; + + +static void +brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits) +{ + int i; + + for (i = 0; i < 32; i++) { + if (bit_map[i].bit == 0) + return; + + if (bit_map[i].bit & bits) + bit_map[i].count++; + } +} + +static void +brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits) +{ + int i; + + for (i = 0; i < 32; i++) { + if (bit_map[i].bit == 0) + return; + + fprintf(stderr, "0x%08x: %12d (%s)\n", + bit_map[i].bit, bit_map[i].count, bit_map[i].name); + } +} + /*********************************************************************** * Emit all state: */ @@ -246,6 +358,7 @@ void brw_upload_state(struct brw_context *brw) { struct brw_state_flags *state = &brw->state.dirty; int i; + static int dirty_count = 0; brw_clear_validated_bos(brw); @@ -301,6 +414,18 @@ void brw_upload_state(struct brw_context *brw) } } + if (INTEL_DEBUG & DEBUG_STATE) { + brw_update_dirty_count(mesa_bits, state->mesa); + brw_update_dirty_count(brw_bits, state->brw); + brw_update_dirty_count(cache_bits, state->cache); + if (dirty_count++ % 1000 == 0) { + brw_print_dirty_count(mesa_bits, state->mesa); + brw_print_dirty_count(brw_bits, state->brw); + brw_print_dirty_count(cache_bits, state->cache); + fprintf(stderr, "\n"); + } + } + if (!brw->intel.Fallback) memset(state, 0, sizeof(*state)); } diff --git a/src/mesa/drivers/dri/i965/brw_vtbl.c b/src/mesa/drivers/dri/i965/brw_vtbl.c index 2d4c812..f7293ef 100644 --- a/src/mesa/drivers/dri/i965/brw_vtbl.c +++ b/src/mesa/drivers/dri/i965/brw_vtbl.c @@ -171,8 +171,6 @@ static void brw_note_unlock( struct intel_context *intel ) struct brw_context *brw = brw_context(&intel->ctx); brw_state_cache_check_size(brw); - - brw_context(&intel->ctx)->state.dirty.brw |= BRW_NEW_LOCK; } diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 361312c..bad7679 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -230,12 +230,6 @@ static void brw_wm_populate_key( struct brw_context *brw, lookup |= IZ_STENCIL_WRITE_ENABLE_BIT; } - /* XXX: when should this be disabled? - */ - if (1) - lookup |= IZ_EARLY_DEPTH_TEST_BIT; - - line_aa = AA_NEVER; /* _NEW_LINE, _NEW_POLYGON, BRW_NEW_REDUCED_PRIMITIVE */ diff --git a/src/mesa/drivers/dri/i965/brw_wm.h b/src/mesa/drivers/dri/i965/brw_wm.h index 896390c..ded0796 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.h +++ b/src/mesa/drivers/dri/i965/brw_wm.h @@ -49,8 +49,7 @@ #define IZ_DEPTH_TEST_ENABLE_BIT 0x8 #define IZ_STENCIL_WRITE_ENABLE_BIT 0x10 #define IZ_STENCIL_TEST_ENABLE_BIT 0x20 -#define IZ_EARLY_DEPTH_TEST_BIT 0x40 -#define IZ_BIT_MAX 0x80 +#define IZ_BIT_MAX 0x40 #define AA_NEVER 0 #define AA_SOMETIMES 1 diff --git a/src/mesa/drivers/dri/i965/brw_wm_fp.c b/src/mesa/drivers/dri/i965/brw_wm_fp.c index d3e926c..7f7b957 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_fp.c +++ b/src/mesa/drivers/dri/i965/brw_wm_fp.c @@ -426,10 +426,6 @@ static struct prog_src_register search_or_add_param5(struct brw_wm_compile *c, idx = _mesa_add_state_reference( paramList, tokens ); - /* Recalculate state dependency: - */ - c->fp->param_state = paramList->StateFlags; - return src_reg(PROGRAM_STATE_VAR, idx); } diff --git a/src/mesa/drivers/dri/i965/brw_wm_iz.c b/src/mesa/drivers/dri/i965/brw_wm_iz.c index 0bb5d5b..bd60ac9 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_iz.c +++ b/src/mesa/drivers/dri/i965/brw_wm_iz.c @@ -52,70 +52,6 @@ const struct { { { P, 0, 0, 0, 0 }, { P, 0, 0, 0, 0 }, - { C, 0, 1, 0, 0 }, - { C, 0, 1, 0, 0 }, - { C, 1, 1, 0, 0 }, - { C, 1, 1, 0, 0 }, - { C, 0, 1, 0, 0 }, - { C, 0, 1, 0, 0 }, - { C, 1, 1, 1, 0 }, - { C, 1, 1, 1, 0 }, - { C, 0, 1, 1, 0 }, - { C, 0, 1, 1, 0 }, - { C, 1, 1, 1, 0 }, - { C, 1, 1, 1, 0 }, - { C, 0, 1, 1, 0 }, - { C, 0, 1, 1, 0 }, - { P, 0, 0, 0, 0 }, - { P, 0, 0, 0, 0 }, - { C, 0, 1, 0, 0 }, - { C, 0, 1, 0, 0 }, - { C, 1, 1, 0, 0 }, - { C, 1, 1, 0, 0 }, - { C, 0, 1, 0, 0 }, - { C, 0, 1, 0, 0 }, - { C, 1, 1, 1, 0 }, - { C, 1, 1, 1, 0 }, - { C, 0, 1, 1, 0 }, - { C, 0, 1, 1, 0 }, - { C, 1, 1, 1, 0 }, - { C, 1, 1, 1, 0 }, - { C, 0, 1, 1, 0 }, - { C, 0, 1, 1, 0 }, - { C, 0, 0, 0, 1 }, - { C, 0, 0, 0, 1 }, - { C, 0, 1, 0, 1 }, - { C, 0, 1, 0, 1 }, - { C, 1, 1, 0, 1 }, - { C, 1, 1, 0, 1 }, - { C, 0, 1, 0, 1 }, - { C, 0, 1, 0, 1 }, - { C, 1, 1, 1, 1 }, - { C, 1, 1, 1, 1 }, - { C, 0, 1, 1, 1 }, - { C, 0, 1, 1, 1 }, - { C, 1, 1, 1, 1 }, - { C, 1, 1, 1, 1 }, - { C, 0, 1, 1, 1 }, - { C, 0, 1, 1, 1 }, - { C, 0, 0, 0, 1 }, - { C, 0, 0, 0, 1 }, - { C, 0, 1, 0, 1 }, - { C, 0, 1, 0, 1 }, - { C, 1, 1, 0, 1 }, - { C, 1, 1, 0, 1 }, - { C, 0, 1, 0, 1 }, - { C, 0, 1, 0, 1 }, - { C, 1, 1, 1, 1 }, - { C, 1, 1, 1, 1 }, - { C, 0, 1, 1, 1 }, - { C, 0, 1, 1, 1 }, - { C, 1, 1, 1, 1 }, - { C, 1, 1, 1, 1 }, - { C, 0, 1, 1, 1 }, - { C, 0, 1, 1, 1 }, - { P, 0, 0, 0, 0 }, - { P, 0, 0, 0, 0 }, { P, 0, 0, 0, 0 }, { P, 0, 0, 0, 0 }, { P, 0, 0, 0, 0 }, diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c index fd46161..5302405 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_state.c @@ -88,7 +88,7 @@ wm_unit_populate_key(struct brw_context *brw, struct brw_wm_unit_key *key) /* BRW_NEW_CURBE_OFFSETS */ key->curbe_offset = brw->curbe.wm_start; - /* CACHE_NEW_SURFACE */ + /* BRW_NEW_NR_SURFACEs */ key->nr_surfaces = brw->wm.nr_surfaces; /* CACHE_NEW_SAMPLER */ @@ -281,10 +281,9 @@ const struct brw_tracked_state brw_wm_unit = { .brw = (BRW_NEW_FRAGMENT_PROGRAM | BRW_NEW_CURBE_OFFSETS | - BRW_NEW_LOCK), + BRW_NEW_NR_SURFACES), - .cache = (CACHE_NEW_SURFACE | - CACHE_NEW_WM_PROG | + .cache = (CACHE_NEW_WM_PROG | CACHE_NEW_SAMPLER) }, .prepare = upload_wm_unit, diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 3790b50..63e14cc 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -438,6 +438,7 @@ static void prepare_wm_surfaces(struct brw_context *brw ) GLcontext *ctx = &brw->intel.ctx; struct intel_context *intel = &brw->intel; GLuint i; + int old_nr_surfaces; if (brw->state.nr_draw_regions > 1) { for (i = 0; i < brw->state.nr_draw_regions; i++) { @@ -448,6 +449,7 @@ static void prepare_wm_surfaces(struct brw_context *brw ) brw_update_region_surface(brw, brw->state.draw_regions[0], 0, GL_TRUE); } + old_nr_surfaces = brw->wm.nr_surfaces; brw->wm.nr_surfaces = MAX_DRAW_BUFFERS; for (i = 0; i < BRW_MAX_TEX_UNIT; i++) { @@ -473,6 +475,9 @@ static void prepare_wm_surfaces(struct brw_context *brw ) dri_bo_unreference(brw->wm.bind_bo); brw->wm.bind_bo = brw_wm_get_binding_table(brw); + + if (brw->wm.nr_surfaces != old_nr_surfaces) + brw->state.dirty.brw |= BRW_NEW_NR_SURFACES; } diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 60028f0..ee43ed7 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -184,6 +184,7 @@ struct intel_context GLuint id; uint32_t primitive; /**< Current hardware primitive type */ void (*flush) (struct intel_context *); + GLubyte *start_ptr; /**< for i8xx */ dri_bo *vb_bo; uint8_t *vb; unsigned int start_offset; /**< Byte offset of primitive sequence */ diff --git a/src/mesa/drivers/dri/intel/intel_reg.h b/src/mesa/drivers/dri/intel/intel_reg.h index 68d8a05..57ac8f0 100644 --- a/src/mesa/drivers/dri/intel/intel_reg.h +++ b/src/mesa/drivers/dri/intel/intel_reg.h @@ -71,14 +71,14 @@ /** @{ * 915 definitions */ -#define S0_VB_OFFSET_MASK 0xffffffc +#define S0_VB_OFFSET_MASK 0xffffffc0 #define S0_AUTO_CACHE_INV_DISABLE (1<<0) /** @} */ /** @{ * 830 definitions */ -#define S0_VB_OFFSET_MASK_830 0xffffff8 +#define S0_VB_OFFSET_MASK_830 0xffffff80 #define S0_VB_PITCH_SHIFT_830 1 #define S0_VB_ENABLE_830 (1<<0) /** @} */ diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index cf09fad..61b55b9 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -461,6 +461,7 @@ intelCreateContext(const __GLcontextModes * mesaVis, sharedContextPrivate); } } else { + intelScreen->no_vbo = GL_TRUE; return i830CreateContext(mesaVis, driContextPriv, sharedContextPrivate); } #else diff --git a/src/mesa/drivers/dri/intel/intel_screen.h b/src/mesa/drivers/dri/intel/intel_screen.h index fc913da..91f0d6d 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.h +++ b/src/mesa/drivers/dri/intel/intel_screen.h @@ -77,6 +77,7 @@ typedef struct GLboolean no_hw; + GLboolean no_vbo; int ttm; dri_bufmgr *bufmgr; diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index 36446ef..dd932ae 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -98,7 +98,9 @@ do_copy_texsubimage(struct intel_context *intel, get_teximage_source(intel, internalFormat); if (!intelImage->mt || !src) { - DBG("%s fail %p %p\n", __FUNCTION__, intelImage->mt, src); + if (INTEL_DEBUG & DEBUG_FALLBACKS) + fprintf(stderr, "%s fail %p %p\n", + __FUNCTION__, intelImage->mt, src); return GL_FALSE; } |