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| author | Samuel Iglesias Gonsálvez <siglesias@igalia.com> | 2015-12-15 12:51:48 +0100 |
|---|---|---|
| committer | Samuel Iglesias Gonsálvez <siglesias@igalia.com> | 2016-01-04 07:52:24 +0100 |
| commit | 8cf2e892fca20c4776b4a07c39918343cb2d4e0e (patch) | |
| tree | bffd4384a454c6c752adb109a1c1cc9bb2b6016a /src/mesa/drivers | |
| parent | 86fa48426cef42d7224139603b52a7d16bd35eb5 (diff) | |
| download | external_mesa3d-8cf2e892fca20c4776b4a07c39918343cb2d4e0e.zip external_mesa3d-8cf2e892fca20c4776b4a07c39918343cb2d4e0e.tar.gz external_mesa3d-8cf2e892fca20c4776b4a07c39918343cb2d4e0e.tar.bz2 | |
i965/wm: use proper API buffer size for the surfaces.
Commit 5bb5eeea fixes a bug indicating that the surfaces should have the
API buffer size. Hovewer it picked the wrong value.
This patch adds a new variable, which takes into account
glBindBufferRange() values. This patch fixes the following CTS
regressions:
ES31-CTS.shader_storage_buffer_object.advanced-unsizedArrayLength-cs-std430-vec-bindrangeOffset
ES31-CTS.shader_storage_buffer_object.advanced-unsizedArrayLength-cs-std430-vec-bindrangeSize
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Marta Lofstedt <marta.lofstedt@intel.com>
Diffstat (limited to 'src/mesa/drivers')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_buffer_objects.c | 1 |
2 files changed, 9 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 76dc577..7da4a40 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -946,12 +946,14 @@ brw_upload_ubo_surfaces(struct brw_context *brw, } else { struct intel_buffer_object *intel_bo = intel_buffer_object(binding->BufferObject); + GLsizeiptrARB size = MIN2(binding->BufferObject->BufferRangeSize, + binding->BufferObject->Size - binding->Offset); drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo, binding->Offset, - binding->BufferObject->Size - binding->Offset); + size); brw_create_constant_surface(brw, bo, binding->Offset, - binding->BufferObject->Size - binding->Offset, + size, &ubo_surf_offsets[i]); } } @@ -968,12 +970,14 @@ brw_upload_ubo_surfaces(struct brw_context *brw, } else { struct intel_buffer_object *intel_bo = intel_buffer_object(binding->BufferObject); + GLsizeiptrARB size = MIN2(binding->BufferObject->BufferRangeSize, + binding->BufferObject->Size - binding->Offset); drm_intel_bo *bo = intel_bufferobj_buffer(brw, intel_bo, binding->Offset, - binding->BufferObject->Size - binding->Offset); + size); brw_create_buffer_surface(brw, bo, binding->Offset, - binding->BufferObject->Size - binding->Offset, + size, &ssbo_surf_offsets[i]); } } diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c index 7a5b3fc..b26c939 100644 --- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c @@ -198,6 +198,7 @@ brw_buffer_data(struct gl_context *ctx, (void) target; intel_obj->Base.Size = size; + intel_obj->Base.BufferRangeSize = size; intel_obj->Base.Usage = usage; intel_obj->Base.StorageFlags = storageFlags; |