i965: Update multisampling state for Broadwell.

On previous platforms, 3DSTATE_MULTISAMPLE contained the number of
samples, pixel location, and the positions of each sample within a pixel
for each multisampling mode (4x and 8x).  It was also a non-pipelined
command, presumably since changing the sample positions is fairly
drastic.

Broadwell improves upon this by splitting the sample positions out into
a separate non-pipelined state packet, 3DSTATE_SAMPLE_PATTERN.  With
that removed, 3DSTATE_MULTISAMPLE becomes a pipelined state packet.

Broadwell also supports 2x and 16x multisampling, in addition to the 4x
and 8x supported by Gen7.  This patch, however, does not implement 2x
and 16x.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

7 files changed, 135 insertions, 1 deletions

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources b/src/mesa/drivers/dri/i965/Makefile.sources
index dcc8c5e..f47ea6b 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -150,6 +150,7 @@ i965_FILES = \
 	gen8_generator.cpp \
 	gen8_instruction.c \
 	gen8_misc_state.c \
+	gen8_multisample_state.c \
 	gen8_sf_state.c \
 	gen8_sol_state.c \
 	gen8_surface_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index 47f94b6..afa3350 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1732,6 +1732,10 @@ gen6_get_sample_position(struct gl_context *ctx,
                          GLuint index,
                          GLfloat *result);
 
+/* gen8_multisample_state.c */
+void gen8_emit_3dstate_multisample(struct brw_context *brw, unsigned num_samp);
+void gen8_emit_3dstate_sample_pattern(struct brw_context *brw);
+
 /* gen7_urb.c */
 void
 gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 52af08b..e286942 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2024,12 +2024,17 @@ enum brw_wm_barycentric_interp_mode {
 /* DW3: SVB maximum index */
 
 #define _3DSTATE_MULTISAMPLE			0x790d /* GEN6+ */
+#define GEN8_3DSTATE_MULTISAMPLE		0x780d /* GEN8+ */
 /* DW1 */
 # define MS_PIXEL_LOCATION_CENTER			(0 << 4)
 # define MS_PIXEL_LOCATION_UPPER_LEFT			(1 << 4)
 # define MS_NUMSAMPLES_1				(0 << 1)
+# define MS_NUMSAMPLES_2				(1 << 1)
 # define MS_NUMSAMPLES_4				(2 << 1)
 # define MS_NUMSAMPLES_8				(3 << 1)
+# define MS_NUMSAMPLES_16				(4 << 1)
+
+#define _3DSTATE_SAMPLE_PATTERN                 0x791c
 
 #define _3DSTATE_STENCIL_BUFFER			0x790e /* ILK, SNB */
 #define _3DSTATE_HIER_DEPTH_BUFFER		0x790f /* ILK, SNB */
diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h
index 865448c..40a152f 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -134,6 +134,7 @@ extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_disable_stages;
 extern const struct brw_tracked_state gen8_index_buffer;
+extern const struct brw_tracked_state gen8_multisample_state;
 extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_ps_extra;
 extern const struct brw_tracked_state gen8_ps_state;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 044a30a..5ecebf5 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -294,7 +294,7 @@ static const struct brw_tracked_state *gen8_atoms[] =
    &brw_fs_samplers,
    &brw_vs_samplers,
    &brw_gs_samplers,
-   &gen6_multisample_state,
+   &gen8_multisample_state,
 
    &gen8_disable_stages,
    &gen8_vs_state,
@@ -342,6 +342,10 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
       return;
 
    brw_upload_invariant_state(brw);
+
+   if (brw->gen >= 8) {
+      gen8_emit_3dstate_sample_pattern(brw);
+   }
 }
 
 void brw_init_state( struct brw_context *brw )
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index 2f2f575..f28e880 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -64,6 +64,8 @@ gen6_emit_3dstate_multisample(struct brw_context *brw,
    uint32_t sample_positions_3210 = 0;
    uint32_t sample_positions_7654 = 0;
 
+   assert(brw->gen < 8);
+
    switch (num_samples) {
    case 0:
    case 1:
diff --git a/src/mesa/drivers/dri/i965/gen8_multisample_state.c b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
new file mode 100644
index 0000000..ad273e4
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/gen8_multisample_state.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "intel_batchbuffer.h"
+
+#include "brw_context.h"
+#include "brw_defines.h"
+#include "brw_multisample_state.h"
+
+/**
+ * 3DSTATE_MULTISAMPLE
+ */
+void
+gen8_emit_3dstate_multisample(struct brw_context *brw, unsigned num_samples)
+{
+   uint32_t number_of_multisamples = 0;
+
+   switch (num_samples) {
+   case 0:
+   case 1:
+      number_of_multisamples = MS_NUMSAMPLES_1;
+      break;
+   case 2:
+      number_of_multisamples = MS_NUMSAMPLES_2;
+      break;
+   case 4:
+      number_of_multisamples = MS_NUMSAMPLES_4;
+      break;
+   case 8:
+      number_of_multisamples = MS_NUMSAMPLES_8;
+      break;
+   case 16:
+      number_of_multisamples = MS_NUMSAMPLES_16;
+      break;
+   default:
+      assert(!"Unrecognized num_samples in gen8_emit_3dstate_multisample");
+      break;
+   }
+
+   BEGIN_BATCH(2);
+   OUT_BATCH(GEN8_3DSTATE_MULTISAMPLE << 16 | (2 - 2));
+   OUT_BATCH(MS_PIXEL_LOCATION_CENTER | number_of_multisamples);
+   ADVANCE_BATCH();
+}
+
+/**
+ * 3DSTATE_SAMPLE_PATTERN
+ */
+void
+gen8_emit_3dstate_sample_pattern(struct brw_context *brw)
+{
+   BEGIN_BATCH(9);
+   OUT_BATCH(_3DSTATE_SAMPLE_PATTERN << 16 | (9 - 2));
+
+   /* 16x MSAA
+    * XXX: Need to program these.
+    */
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+
+   /* 8x MSAA */
+   OUT_BATCH(brw_multisample_positions_8x[1]); /* sample positions 7654 */
+   OUT_BATCH(brw_multisample_positions_8x[0]); /* sample positions 3210 */
+
+   /* 4x MSAA */
+   OUT_BATCH(brw_multisample_positions_4x[0]);
+
+   /* 2x and 1x MSAA patterns
+    * XXX: need to program 2x.
+    */
+   OUT_BATCH(0x00880000);
+   ADVANCE_BATCH();
+}
+
+
+static void
+upload_multisample_state(struct brw_context *brw)
+{
+   struct gl_context *ctx = &brw->ctx;
+
+   /* _NEW_BUFFERS, _NEW_MULTISAMPLE */
+   unsigned num_samples = ctx->DrawBuffer->Visual.samples;
+
+   gen8_emit_3dstate_multisample(brw, num_samples);
+   gen6_emit_3dstate_sample_mask(brw, gen6_determine_sample_mask(brw));
+}
+
+const struct brw_tracked_state gen8_multisample_state = {
+   .dirty = {
+      .mesa = _NEW_BUFFERS | _NEW_MULTISAMPLE,
+      .brw = BRW_NEW_CONTEXT,
+      .cache = 0
+   },
+   .emit = upload_multisample_state
+};