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| author | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-10-10 11:44:43 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <nicolai.haehnle@amd.com> | 2016-10-13 15:41:33 +0200 |
| commit | 15fc74905b64ab41e47d5b50407596ceaeced638 (patch) | |
| tree | d43048855c419e527f6f72272f4408a5ca672051 /src/mesa/state_tracker | |
| parent | 1d7685e52ca64f6fcc66b8816b5adb8513b4ae18 (diff) | |
| download | external_mesa3d-15fc74905b64ab41e47d5b50407596ceaeced638.zip external_mesa3d-15fc74905b64ab41e47d5b50407596ceaeced638.tar.gz external_mesa3d-15fc74905b64ab41e47d5b50407596ceaeced638.tar.bz2 | |
st/glsl_to_tgsi: remove unnecessary ir_instruction argument from get_opcode
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'src/mesa/state_tracker')
| -rw-r--r-- | src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index be0aa2e..fd2485d 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -527,7 +527,7 @@ public: st_src_reg src2 = undef_src, st_src_reg src3 = undef_src); - unsigned get_opcode(ir_instruction *ir, unsigned op, + unsigned get_opcode(unsigned op, st_dst_reg dst, st_src_reg src0, st_src_reg src1); @@ -669,7 +669,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op, int num_reladdr = 0, i, j; bool dst_is_64bit[2]; - op = get_opcode(ir, op, dst, src0, src1); + op = get_opcode(op, dst, src0, src1); /* If we have to do relative addressing, we want to load the ARL * reg directly for one of the regs, and preload the other reladdr @@ -900,7 +900,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op, * based on the operands and input opcode, then emits the result. */ unsigned -glsl_to_tgsi_visitor::get_opcode(ir_instruction *ir, unsigned op, +glsl_to_tgsi_visitor::get_opcode(unsigned op, st_dst_reg dst, st_src_reg src0, st_src_reg src1) { |