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author | Alan Hourihane <alanh@tungstengraphics.com> | 2003-12-07 23:53:32 +0000 |
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committer | Alan Hourihane <alanh@tungstengraphics.com> | 2003-12-07 23:53:32 +0000 |
commit | 99ef0a03292e7dc6aa2465aaaa620f394d2c286b (patch) | |
tree | 124750efb73a4fca431d5407a05ae3725ce27c55 /src/mesa | |
parent | 273e52f86fa41564f573c8e84d013f995e01a8f0 (diff) | |
download | external_mesa3d-99ef0a03292e7dc6aa2465aaaa620f394d2c286b.zip external_mesa3d-99ef0a03292e7dc6aa2465aaaa620f394d2c286b.tar.gz external_mesa3d-99ef0a03292e7dc6aa2465aaaa620f394d2c286b.tar.bz2 |
merge some more of the radeon DRI driver from the DRI trunk
Diffstat (limited to 'src/mesa')
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_context.c | 4 | ||||
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_context.h | 1 | ||||
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_ioctl.c | 5 | ||||
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_lock.c | 3 | ||||
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_screen.c | 20 | ||||
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_screen.h | 1 | ||||
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_state.c | 7 | ||||
-rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_state_init.c | 35 |
8 files changed, 59 insertions, 17 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c b/src/mesa/drivers/dri/radeon/radeon_context.c index 3ca109a..2cd09b1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.c +++ b/src/mesa/drivers/dri/radeon/radeon_context.c @@ -231,7 +231,7 @@ static const struct dri_debug_control debug_control[] = static int -get_ust_nop( uint64_t * ust ) +get_ust_nop( int64_t * ust ) { *ust = 1; return 0; @@ -250,7 +250,7 @@ radeonCreateContext( const __GLcontextModes *glVisual, radeonContextPtr rmesa; GLcontext *ctx, *shareCtx; int i; - int tcl_mode, fthrottle_mode, preferred_bpt; + int tcl_mode, fthrottle_mode; assert(glVisual); assert(driContextPriv); diff --git a/src/mesa/drivers/dri/radeon/radeon_context.h b/src/mesa/drivers/dri/radeon/radeon_context.h index a0bf84c..64373e1 100644 --- a/src/mesa/drivers/dri/radeon/radeon_context.h +++ b/src/mesa/drivers/dri/radeon/radeon_context.h @@ -97,6 +97,7 @@ typedef void (*radeon_point_func)( radeonContextPtr, struct radeon_colorbuffer_state { GLuint clear; GLint drawOffset, drawPitch; + int roundEnable; }; diff --git a/src/mesa/drivers/dri/radeon/radeon_ioctl.c b/src/mesa/drivers/dri/radeon/radeon_ioctl.c index 4e1f451..d25a7d6 100644 --- a/src/mesa/drivers/dri/radeon/radeon_ioctl.c +++ b/src/mesa/drivers/dri/radeon/radeon_ioctl.c @@ -803,7 +803,7 @@ void radeonCopyBuffer( const __DRIdrawablePrivate *dPriv ) radeonContextPtr rmesa; GLint nbox, i, ret; GLboolean missed_target; - uint64_t ust; + int64_t ust; assert(dPriv); assert(dPriv->driContextPriv); @@ -923,7 +923,8 @@ void radeonPageFlip( const __DRIdrawablePrivate *dPriv ) } RADEON_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset; + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset + + rmesa->radeonScreen->fbLocation; rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; } diff --git a/src/mesa/drivers/dri/radeon/radeon_lock.c b/src/mesa/drivers/dri/radeon/radeon_lock.c index daf001e..fb28515 100644 --- a/src/mesa/drivers/dri/radeon/radeon_lock.c +++ b/src/mesa/drivers/dri/radeon/radeon_lock.c @@ -73,7 +73,8 @@ radeonUpdatePageFlipping( radeonContextPtr rmesa ) } RADEON_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset; + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = rmesa->state.color.drawOffset + + rmesa->radeonScreen->fbLocation; rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; } diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 8f2042a..3bb7090 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -77,6 +77,7 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv ) { radeonScreenPtr screen; RADEONDRIPtr dri_priv = (RADEONDRIPtr)sPriv->pDevPriv; + unsigned char *RADEONMMIO; if ( ! driCheckDriDdxDrmVersions( sPriv, "Radeon", 4, 0, 4, 0, 1, 3 ) ) return NULL; @@ -137,6 +138,8 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv ) return NULL; } + RADEONMMIO = screen->mmio.map; + screen->status.handle = dri_priv->statusHandle; screen->status.size = dri_priv->statusSize; if ( drmMap( sPriv->fd, @@ -161,8 +164,6 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv ) } if ( dri_priv->gartTexHandle && dri_priv->gartTexMapSize ) { - unsigned char *RADEONMMIO = screen->mmio.map; - screen->gartTextures.handle = dri_priv->gartTexHandle; screen->gartTextures.size = dri_priv->gartTexMapSize; if ( drmMap( sPriv->fd, @@ -203,6 +204,18 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->cpp = dri_priv->bpp / 8; screen->AGPMode = dri_priv->AGPMode; + screen->fbLocation = ( INREG( RADEON_MC_FB_LOCATION ) & 0xffff ) << 16; + + if ( sPriv->drmMinor >= 10 ) { + drmRadeonSetParam sp; + + sp.param = RADEON_SETPARAM_FB_LOCATION; + sp.value = screen->fbLocation; + + drmCommandWrite( sPriv->fd, DRM_RADEON_SETPARAM, + &sp, sizeof( sp ) ); + } + screen->frontOffset = dri_priv->frontOffset; screen->frontPitch = dri_priv->frontPitch; screen->backOffset = dri_priv->backOffset; @@ -210,7 +223,8 @@ radeonScreenPtr radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->depthOffset = dri_priv->depthOffset; screen->depthPitch = dri_priv->depthPitch; - screen->texOffset[RADEON_CARD_HEAP] = dri_priv->textureOffset; + screen->texOffset[RADEON_CARD_HEAP] = dri_priv->textureOffset + + screen->fbLocation; screen->texSize[RADEON_CARD_HEAP] = dri_priv->textureSize; screen->logTexGranularity[RADEON_CARD_HEAP] = dri_priv->log2TexGran; diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h index 133c363..4a0f6d4 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.h +++ b/src/mesa/drivers/dri/radeon/radeon_screen.h @@ -68,6 +68,7 @@ typedef struct { int AGPMode; unsigned int irq; /* IRQ number (0 means none) */ + unsigned int fbLocation; unsigned int frontOffset; unsigned int frontPitch; unsigned int backOffset; diff --git a/src/mesa/drivers/dri/radeon/radeon_state.c b/src/mesa/drivers/dri/radeon/radeon_state.c index c15f341..2772ca9 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state.c +++ b/src/mesa/drivers/dri/radeon/radeon_state.c @@ -1626,8 +1626,9 @@ static void radeonDrawBuffer( GLcontext *ctx, GLenum mode ) _swrast_DrawBuffer(ctx, mode); RADEON_STATECHANGE( rmesa, ctx ); - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = (rmesa->state.color.drawOffset & - RADEON_COLOROFFSET_MASK); + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset + + rmesa->radeonScreen->fbLocation) + & RADEON_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = rmesa->state.color.drawPitch; } @@ -1734,8 +1735,10 @@ static void radeonEnable( GLcontext *ctx, GLenum cap, GLboolean state ) RADEON_STATECHANGE(rmesa, ctx ); if ( state ) { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~rmesa->state.color.roundEnable; } else { rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] &= ~RADEON_DITHER_ENABLE; + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable; } break; diff --git a/src/mesa/drivers/dri/radeon/radeon_state_init.c b/src/mesa/drivers/dri/radeon/radeon_state_init.c index 0b2a108..2aa8dbe 100644 --- a/src/mesa/drivers/dri/radeon/radeon_state_init.c +++ b/src/mesa/drivers/dri/radeon/radeon_state_init.c @@ -46,6 +46,8 @@ #include "radeon_swtcl.h" #include "radeon_vtxfmt.h" +#include "xmlpool.h" + /* ============================================================= * State initialization */ @@ -322,7 +324,7 @@ void radeonInitState( radeonContextPtr rmesa ) RADEON_DST_BLEND_GL_ZERO ); rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] = - rmesa->radeonScreen->depthOffset; + rmesa->radeonScreen->depthOffset + rmesa->radeonScreen->fbLocation; rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] = ((rmesa->radeonScreen->depthPitch & @@ -344,10 +346,28 @@ void radeonInitState( radeonContextPtr rmesa ) color_fmt | (1<<15)); - rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; - - rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = (rmesa->state.color.drawOffset & - RADEON_COLOROFFSET_MASK); + switch ( driQueryOptioni( &rmesa->optionCache, "dither_mode" ) ) { + case DRI_CONF_DITHER_XERRORDIFFRESET: + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_INIT; + break; + case DRI_CONF_DITHER_ORDERED: + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_SCALE_DITHER_ENABLE; + break; + } + if ( driQueryOptioni( &rmesa->optionCache, "round_mode" ) == + DRI_CONF_ROUND_ROUND ) + rmesa->state.color.roundEnable = RADEON_ROUND_ENABLE; + else + rmesa->state.color.roundEnable = 0; + if ( driQueryOptioni (&rmesa->optionCache, "color_reduction" ) == + DRI_CONF_COLOR_REDUCTION_DITHER ) + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= RADEON_DITHER_ENABLE; + else + rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->state.color.roundEnable; + + rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((rmesa->state.color.drawOffset + + rmesa->radeonScreen->fbLocation) + & RADEON_COLOROFFSET_MASK); rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((rmesa->state.color.drawPitch & RADEON_COLORPITCH_MASK) | @@ -421,8 +441,9 @@ void radeonInitState( radeonContextPtr rmesa ) (2 << RADEON_TXFORMAT_WIDTH_SHIFT) | (2 << RADEON_TXFORMAT_HEIGHT_SHIFT)); - /* FIXME: What is this magic value? */ - rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = 0x2000 << (2 * i); + /* Initialize the texture offset to the start of the card texture heap */ + rmesa->hw.tex[i].cmd[TEX_PP_TXOFFSET] = + rmesa->radeonScreen->texOffset[RADEON_CARD_HEAP]; rmesa->hw.tex[i].cmd[TEX_PP_BORDER_COLOR] = 0; rmesa->hw.tex[i].cmd[TEX_PP_TXCBLEND] = |