intel/i965: make gen_device_info mutable

Make gen_device_info a mutable structure so we can update the fields that
can be refined by querying the kernel (like subslices and EU numbers).

This patch does not make any functional change, it just makes
gen_get_device_info() fill a structure rather than returning a const
pointer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

18 files changed, 52 insertions, 53 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_clip.c b/src/mesa/drivers/dri/i965/brw_clip.c
index 1d2070b..1134fa4 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.c
+++ b/src/mesa/drivers/dri/i965/brw_clip.c
@@ -61,7 +61,7 @@ static void compile_clip_prog( struct brw_context *brw,
 
    /* Begin the compilation:
     */
-   brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx);
+   brw_init_codegen(&brw->screen->devinfo, &c.func, mem_ctx);
 
    c.func.single_program_flow = 1;
 
@@ -116,7 +116,7 @@ static void compile_clip_prog( struct brw_context *brw,
 
    if (unlikely(INTEL_DEBUG & DEBUG_CLIP)) {
       fprintf(stderr, "clip:\n");
-      brw_disassemble(brw->screen->devinfo, c.func.store,
+      brw_disassemble(&brw->screen->devinfo, c.func.store,
                       0, program_size, stderr);
       fprintf(stderr, "\n");
    }
diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index 908eb6d..9b72e84 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -207,7 +207,7 @@ intel_texture_view_requires_resolve(struct brw_context *brw,
 
    const uint32_t brw_format = brw_format_for_mesa_format(intel_tex->_Format);
 
-   if (isl_format_supports_lossless_compression(brw->screen->devinfo,
+   if (isl_format_supports_lossless_compression(&brw->screen->devinfo,
                                                 brw_format))
       return false;
 
@@ -806,7 +806,7 @@ brw_initialize_cs_context_constants(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
    const struct intel_screen *screen = brw->screen;
-   const struct gen_device_info *devinfo = screen->devinfo;
+   const struct gen_device_info *devinfo = &screen->devinfo;
 
    /* FINISHME: Do this for all platforms that the kernel supports */
    if (brw->is_cherryview &&
@@ -919,7 +919,7 @@ brwCreateContext(gl_api api,
 {
    struct gl_context *shareCtx = (struct gl_context *) sharedContextPrivate;
    struct intel_screen *screen = driContextPriv->driScreenPriv->driverPrivate;
-   const struct gen_device_info *devinfo = screen->devinfo;
+   const struct gen_device_info *devinfo = &screen->devinfo;
    struct dd_function_table functions;
 
    /* Only allow the __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS flag if the kernel
diff --git a/src/mesa/drivers/dri/i965/brw_cs.c b/src/mesa/drivers/dri/i965/brw_cs.c
index a73673f..e79668f8f 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -84,7 +84,7 @@ brw_codegen_cs_prog(struct brw_context *brw,
       prog_data.base.total_shared = prog->Comp.SharedSize;
    }
 
-   assign_cs_binding_table_offsets(brw->screen->devinfo, prog,
+   assign_cs_binding_table_offsets(&brw->screen->devinfo, prog,
                                    &cp->program.Base, &prog_data);
 
    /* Allocate the references to the uniforms that will end up in the
diff --git a/src/mesa/drivers/dri/i965/brw_ff_gs.c b/src/mesa/drivers/dri/i965/brw_ff_gs.c
index 7c878e9..d8eb146 100644
--- a/src/mesa/drivers/dri/i965/brw_ff_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_ff_gs.c
@@ -63,7 +63,7 @@ brw_codegen_ff_gs_prog(struct brw_context *brw,
 
    /* Begin the compilation:
     */
-   brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx);
+   brw_init_codegen(&brw->screen->devinfo, &c.func, mem_ctx);
 
    c.func.single_program_flow = 1;
 
@@ -135,7 +135,7 @@ brw_codegen_ff_gs_prog(struct brw_context *brw,
 
    if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
       fprintf(stderr, "gs:\n");
-      brw_disassemble(brw->screen->devinfo, c.func.store,
+      brw_disassemble(&brw->screen->devinfo, c.func.store,
                       0, program_size, stderr);
       fprintf(stderr, "\n");
     }
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index 2b472c6..93a909c 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -105,7 +105,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
 
    memset(&prog_data, 0, sizeof(prog_data));
 
-   assign_gs_binding_table_offsets(brw->screen->devinfo, prog,
+   assign_gs_binding_table_offsets(&brw->screen->devinfo, prog,
                                    &gp->program.Base, &prog_data);
 
    /* Allocate the references to the uniforms that will end up in the
@@ -139,7 +139,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
       ((1 << gp->program.Base.CullDistanceArraySize) - 1) <<
       gp->program.Base.ClipDistanceArraySize;
 
-   brw_compute_vue_map(brw->screen->devinfo,
+   brw_compute_vue_map(&brw->screen->devinfo,
                        &prog_data.base.vue_map, outputs_written,
                        prog->SeparateShader);
 
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c b/src/mesa/drivers/dri/i965/brw_sf.c
index dd5b4cc..6d8cd74 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -59,7 +59,7 @@ static void compile_sf_prog( struct brw_context *brw,
    mem_ctx = ralloc_context(NULL);
    /* Begin the compilation:
     */
-   brw_init_codegen(brw->screen->devinfo, &c.func, mem_ctx);
+   brw_init_codegen(&brw->screen->devinfo, &c.func, mem_ctx);
 
    c.key = *key;
    c.vue_map = brw->vue_map_geom_out;
@@ -118,7 +118,7 @@ static void compile_sf_prog( struct brw_context *brw,
 
    if (unlikely(INTEL_DEBUG & DEBUG_SF)) {
       fprintf(stderr, "sf:\n");
-      brw_disassemble(brw->screen->devinfo,
+      brw_disassemble(&brw->screen->devinfo,
                       c.func.store, 0, program_size, stderr);
       fprintf(stderr, "\n");
    }
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c b/src/mesa/drivers/dri/i965/brw_state_dump.c
index b1eba6d..1ed8aaa 100644
--- a/src/mesa/drivers/dri/i965/brw_state_dump.c
+++ b/src/mesa/drivers/dri/i965/brw_state_dump.c
@@ -765,7 +765,7 @@ dump_prog_cache(struct brw_context *brw)
 	 }
 
          fprintf(stderr, "%s:\n", name);
-         brw_disassemble(brw->screen->devinfo, brw->cache.bo->virtual,
+         brw_disassemble(&brw->screen->devinfo, brw->cache.bo->virtual,
                          item->offset, item->size, stderr);
       }
    }
diff --git a/src/mesa/drivers/dri/i965/brw_surface_formats.c b/src/mesa/drivers/dri/i965/brw_surface_formats.c
index d99d386..103d3a0 100644
--- a/src/mesa/drivers/dri/i965/brw_surface_formats.c
+++ b/src/mesa/drivers/dri/i965/brw_surface_formats.c
@@ -288,7 +288,7 @@ brw_format_for_mesa_format(mesa_format mesa_format)
 void
 brw_init_surface_formats(struct brw_context *brw)
 {
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct gl_context *ctx = &brw->ctx;
    int gen;
    mesa_format format;
diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index aeaff96..5c3c9a6 100644
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -83,7 +83,7 @@ brw_codegen_tes_prog(struct brw_context *brw,
                      struct brw_tes_prog_key *key)
 {
    const struct brw_compiler *compiler = brw->screen->compiler;
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    struct brw_stage_state *stage_state = &brw->tes.base;
    nir_shader *nir = tep->program.Base.nir;
    struct brw_tes_prog_data prog_data;
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index c637304..a51e4a2 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -112,7 +112,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
    mem_ctx = ralloc_context(NULL);
 
    brw_assign_common_binding_table_offsets(MESA_SHADER_VERTEX,
-                                           brw->screen->devinfo,
+                                           &brw->screen->devinfo,
                                            prog, &vp->program.Base,
                                            &prog_data.base.base, 0);
 
@@ -160,7 +160,7 @@ brw_codegen_vs_prog(struct brw_context *brw,
       ((1 << vp->program.Base.CullDistanceArraySize) - 1) <<
       vp->program.Base.ClipDistanceArraySize;
 
-   brw_compute_vue_map(brw->screen->devinfo,
+   brw_compute_vue_map(&brw->screen->devinfo,
                        &prog_data.base.vue_map, outputs_written,
                        prog ? prog->SeparateShader ||
                               prog->_LinkedShaders[MESA_SHADER_TESS_EVAL]
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 23674f6..ba8e4ad 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -97,7 +97,7 @@ brw_codegen_wm_prog(struct brw_context *brw,
    if (!prog)
       prog_data.base.use_alt_mode = true;
 
-   assign_fs_binding_table_offsets(brw->screen->devinfo, prog,
+   assign_fs_binding_table_offsets(&brw->screen->devinfo, prog,
                                    &fp->program.Base, key, &prog_data);
 
    /* Allocate the references to the uniforms that will end up in the
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index ba6fa52..61a4b94 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -94,7 +94,7 @@ brw_emit_surface_state(struct brw_context *brw,
    surf.dim = get_isl_surf_dim(target);
 
    const enum isl_dim_layout dim_layout =
-      get_isl_dim_layout(brw->screen->devinfo, mt->tiling, target);
+      get_isl_dim_layout(&brw->screen->devinfo, mt->tiling, target);
 
    if (surf.dim_layout != dim_layout) {
       /* The layout of the specified texture target is not compatible with the
@@ -441,7 +441,7 @@ brw_texture_view_sane(const struct brw_context *brw,
    if (!intel_miptree_is_lossless_compressed(brw, mt))
       return true;
 
-   if (isl_format_supports_lossless_compression(brw->screen->devinfo,
+   if (isl_format_supports_lossless_compression(&brw->screen->devinfo,
                                                 format))
       return true;
 
@@ -1075,7 +1075,7 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw,
          const uint32_t surf_index = render_target_start + i;
          const int flags = (_mesa_geometric_layers(fb) > 0 ?
                               INTEL_RENDERBUFFER_LAYERED : 0) |
-                           (brw->draw_aux_buffer_disabled[i] ? 
+                           (brw->draw_aux_buffer_disabled[i] ?
                               INTEL_AUX_BUFFER_DISABLED : 0);
 
 	 if (intel_renderbuffer(fb->_ColorDrawBuffers[i])) {
@@ -1150,7 +1150,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
          if (irb) {
             const unsigned format = brw->render_target_format[
                _mesa_get_render_format(ctx, intel_rb_format(irb))];
-            assert(isl_format_supports_sampling(brw->screen->devinfo,
+            assert(isl_format_supports_sampling(&brw->screen->devinfo,
                                                 format));
 
             /* Override the target of the texture if the render buffer is a
@@ -1577,7 +1577,7 @@ const struct brw_tracked_state brw_cs_image_surfaces = {
 static uint32_t
 get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
 {
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    uint32_t hw_format = brw_format_for_mesa_format(format);
    if (access == GL_WRITE_ONLY) {
       return hw_format;
diff --git a/src/mesa/drivers/dri/i965/gen7_cs_state.c b/src/mesa/drivers/dri/i965/gen7_cs_state.c
index 1aa4b2f..862b915 100644
--- a/src/mesa/drivers/dri/i965/gen7_cs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_cs_state.c
@@ -46,7 +46,7 @@ brw_upload_cs_state(struct brw_context *brw)
    struct brw_stage_state *stage_state = &brw->cs.base;
    struct brw_cs_prog_data *cs_prog_data = brw->cs.prog_data;
    struct brw_stage_prog_data *prog_data = &cs_prog_data->base;
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
 
    if (INTEL_DEBUG & DEBUG_SHADER_TIME) {
       brw_emit_buffer_surface_state(
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index ec494df..ad70491 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -58,7 +58,7 @@ get_pipeline_state_l3_weights(const struct brw_context *brw)
       needs_slm |= prog_data && prog_data->total_shared;
    }
 
-   return gen_get_default_l3_weights(brw->screen->devinfo,
+   return gen_get_default_l3_weights(&brw->screen->devinfo,
                                      needs_dc, needs_slm);
 }
 
@@ -197,7 +197,7 @@ setup_l3_config(struct brw_context *brw, const struct gen_l3_config *cfg)
 static void
 update_urb_size(struct brw_context *brw, const struct gen_l3_config *cfg)
 {
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const unsigned sz = gen_get_l3_config_urb_size(devinfo, cfg);
 
    if (brw->urb.size != sz) {
@@ -230,7 +230,7 @@ emit_l3_state(struct brw_context *brw)
 
    if (dw > dw_threshold && brw->can_do_pipelined_register_writes) {
       const struct gen_l3_config *const cfg =
-         gen_get_l3_config(brw->screen->devinfo, w);
+         gen_get_l3_config(&brw->screen->devinfo, w);
 
       setup_l3_config(brw, cfg);
       update_urb_size(brw, cfg);
@@ -292,7 +292,7 @@ const struct brw_tracked_state gen7_l3_state = {
 void
 gen7_restore_default_l3_config(struct brw_context *brw)
 {
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const struct gen_l3_config *const cfg = gen_get_default_l3_config(devinfo);
 
    if (cfg != brw->l3.config && brw->can_do_pipelined_register_writes) {
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index 707e073..4216af8 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -202,7 +202,7 @@ void
 gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
                 bool gs_present, bool tess_present)
 {
-   const struct gen_device_info *devinfo = brw->screen->devinfo;
+   const struct gen_device_info *devinfo = &brw->screen->devinfo;
    const int push_size_kB =
       (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16;
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 5e19d54..aba203a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -262,7 +262,7 @@ intel_miptree_supports_non_msrt_fast_clear(struct brw_context *brw,
    if (brw->gen >= 9) {
       mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
       const uint32_t brw_format = brw_format_for_mesa_format(linear_format);
-      return isl_format_supports_lossless_compression(brw->screen->devinfo,
+      return isl_format_supports_lossless_compression(&brw->screen->devinfo,
                                                       brw_format);
    } else
       return true;
@@ -3063,7 +3063,7 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
                            struct isl_surf *surf)
 {
    surf->dim = get_isl_surf_dim(mt->target);
-   surf->dim_layout = get_isl_dim_layout(brw->screen->devinfo,
+   surf->dim_layout = get_isl_dim_layout(&brw->screen->devinfo,
                                          mt->tiling, mt->target);
 
    if (mt->num_samples > 1) {
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index d4e34ec..2026e3e 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1088,7 +1088,7 @@ intelCreateBuffer(__DRIscreen *dri_screen,
    if (mesaVis->depthBits == 24) {
       assert(mesaVis->stencilBits == 8);
 
-      if (screen->devinfo->has_hiz_and_separate_stencil) {
+      if (screen->devinfo.has_hiz_and_separate_stencil) {
          rb = intel_create_private_renderbuffer(MESA_FORMAT_Z24_UNORM_X8_UINT,
                                                 num_samples);
          _mesa_add_renderbuffer(fb, BUFFER_DEPTH, &rb->Base.Base);
@@ -1141,7 +1141,7 @@ intelDestroyBuffer(__DRIdrawable * driDrawPriv)
 static void
 intel_detect_sseu(struct intel_screen *screen)
 {
-   assert(screen->devinfo->gen >= 8);
+   assert(screen->devinfo.gen >= 8);
    int ret;
 
    screen->subslice_total = -1;
@@ -1278,13 +1278,13 @@ intel_supported_msaa_modes(const struct intel_screen  *screen)
    static const int gen6_modes[] = {4, 0, -1};
    static const int gen4_modes[] = {0, -1};
 
-   if (screen->devinfo->gen >= 9) {
+   if (screen->devinfo.gen >= 9) {
       return gen9_modes;
-   } else if (screen->devinfo->gen >= 8) {
+   } else if (screen->devinfo.gen >= 8) {
       return gen8_modes;
-   } else if (screen->devinfo->gen >= 7) {
+   } else if (screen->devinfo.gen >= 7) {
       return gen7_modes;
-   } else if (screen->devinfo->gen == 6) {
+   } else if (screen->devinfo.gen == 6) {
       return gen6_modes;
    } else {
       return gen4_modes;
@@ -1309,7 +1309,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
    static const uint8_t multisample_samples[2]  = {4, 8};
 
    struct intel_screen *screen = dri_screen->driverPrivate;
-   const struct gen_device_info *devinfo = screen->devinfo;
+   const struct gen_device_info *devinfo = &screen->devinfo;
    uint8_t depth_bits[4], stencil_bits[4];
    __DRIconfig **configs = NULL;
 
@@ -1431,9 +1431,9 @@ static void
 set_max_gl_versions(struct intel_screen *screen)
 {
    __DRIscreen *dri_screen = screen->driScrnPriv;
-   const bool has_astc = screen->devinfo->gen >= 9;
+   const bool has_astc = screen->devinfo.gen >= 9;
 
-   switch (screen->devinfo->gen) {
+   switch (screen->devinfo.gen) {
    case 9:
    case 8:
       dri_screen->max_gl_core_version = 44;
@@ -1445,7 +1445,7 @@ set_max_gl_versions(struct intel_screen *screen)
       dri_screen->max_gl_core_version = 33;
       dri_screen->max_gl_compat_version = 30;
       dri_screen->max_gl_es1_version = 11;
-      dri_screen->max_gl_es2_version = screen->devinfo->is_haswell ? 31 : 30;
+      dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30;
       break;
    case 6:
       dri_screen->max_gl_core_version = 33;
@@ -1573,8 +1573,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
        return false;
 
    screen->deviceID = drm_intel_bufmgr_gem_get_devid(screen->bufmgr);
-   screen->devinfo = gen_get_device_info(screen->deviceID);
-   if (!screen->devinfo)
+   if (!gen_get_device_info(screen->deviceID, &screen->devinfo))
       return false;
 
    brw_process_intel_debug_variable();
@@ -1582,7 +1581,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
    if (INTEL_DEBUG & DEBUG_BUFMGR)
       dri_bufmgr_set_debug(screen->bufmgr, true);
 
-   if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && screen->devinfo->gen < 7) {
+   if ((INTEL_DEBUG & DEBUG_SHADER_TIME) && screen->devinfo.gen < 7) {
       fprintf(stderr,
               "shader_time debugging requires gen7 (Ivybridge) or better.\n");
       INTEL_DEBUG &= ~DEBUG_SHADER_TIME;
@@ -1632,10 +1631,10 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
    screen->hw_has_timestamp = intel_detect_timestamp(screen);
 
    /* GENs prior to 8 do not support EU/Subslice info */
-   if (screen->devinfo->gen >= 8) {
+   if (screen->devinfo.gen >= 8) {
       intel_detect_sseu(screen);
-   } else if (screen->devinfo->gen == 7) {
-      screen->subslice_total = 1 << (screen->devinfo->gt - 1);
+   } else if (screen->devinfo.gen == 7) {
+      screen->subslice_total = 1 << (screen->devinfo.gt - 1);
    }
 
    const char *force_msaa = getenv("INTEL_FORCE_MSAA");
@@ -1659,7 +1658,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
     *
     * Don't even try on pre-Gen6, since we don't attempt to use contexts there.
     */
-   if (screen->devinfo->gen >= 6) {
+   if (screen->devinfo.gen >= 6) {
       struct drm_i915_reset_stats stats;
       memset(&stats, 0, sizeof(stats));
 
@@ -1678,20 +1677,20 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
     * MI_MATH GPR registers, and version 7 in order to use
     * MI_LOAD_REGISTER_REG (which all users of MI_MATH use).
     */
-   screen->has_mi_math_and_lrr = screen->devinfo->gen >= 8 ||
-                                      (screen->devinfo->is_haswell &&
+   screen->has_mi_math_and_lrr = screen->devinfo.gen >= 8 ||
+                                      (screen->devinfo.is_haswell &&
                                        screen->cmd_parser_version >= 7);
 
    dri_screen->extensions = !screen->has_context_reset_notification
       ? screenExtensions : intelRobustScreenExtensions;
 
    screen->compiler = brw_compiler_create(screen,
-                                               screen->devinfo);
+                                          &screen->devinfo);
    screen->compiler->shader_debug_log = shader_debug_log_mesa;
    screen->compiler->shader_perf_log = shader_perf_log_mesa;
    screen->program_id = 1;
 
-   if (screen->devinfo->has_resource_streamer) {
+   if (screen->devinfo.has_resource_streamer) {
       screen->has_resource_streamer =
         intel_get_boolean(screen, I915_PARAM_HAS_RESOURCE_STREAMER);
    }
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h
index acf319c..51c1d4e 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -40,7 +40,7 @@
 struct intel_screen
 {
    int deviceID;
-   const struct gen_device_info *devinfo;
+   struct gen_device_info devinfo;
 
    __DRIscreen *driScrnPriv;