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| author | Michel Dänzer <michel.daenzer@amd.com> | 2014-09-09 09:55:07 +0900 |
|---|---|---|
| committer | Michel Dänzer <michel@daenzer.net> | 2014-09-10 12:01:10 +0900 |
| commit | 5679ccfcaf8221cc1252e3214e182085dd850d33 (patch) | |
| tree | 19dff2aa7486450bc9c41caded4343d138f38b85 /src | |
| parent | 720cfb6fe9a3dafadf3bc034008f7c5c15973866 (diff) | |
| download | external_mesa3d-5679ccfcaf8221cc1252e3214e182085dd850d33.zip external_mesa3d-5679ccfcaf8221cc1252e3214e182085dd850d33.tar.gz external_mesa3d-5679ccfcaf8221cc1252e3214e182085dd850d33.tar.bz2 | |
r600g,radeonsi: Set RADEON_GEM_NO_CPU_ACCESS flag for tiled BOs
This lets the kernel know that such BOs can be pinned outside of the CPU
accessible part of VRAM.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/gallium/drivers/radeon/r600_buffer_common.c | 1 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 12 | ||||
| -rw-r--r-- | src/gallium/winsys/radeon/drm/radeon_winsys.h | 5 |
3 files changed, 13 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c index d85b64b..227a221 100644 --- a/src/gallium/drivers/radeon/r600_buffer_common.c +++ b/src/gallium/drivers/radeon/r600_buffer_common.c @@ -156,6 +156,7 @@ bool r600_init_resource(struct r600_common_screen *rscreen, rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D) { res->domains = RADEON_DOMAIN_VRAM; flags &= ~RADEON_FLAG_CPU_ACCESS; + flags |= RADEON_FLAG_NO_CPU_ACCESS; } /* Allocate a new resource. */ diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 5a5a2f1..e61e9fd 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -477,11 +477,15 @@ const struct pb_vtbl radeon_bo_vtbl = { }; #ifndef RADEON_GEM_GTT_WC -#define RADEON_GEM_GTT_WC (1 << 2) +#define RADEON_GEM_GTT_WC (1 << 2) #endif -#ifndef RADEON_GTM_CPU_ACCESS +#ifndef RADEON_GEM_CPU_ACCESS /* BO is expected to be accessed by the CPU */ -#define RADEON_GEM_CPU_ACCESS (1 << 3) +#define RADEON_GEM_CPU_ACCESS (1 << 3) +#endif +#ifndef RADEON_GEM_NO_CPU_ACCESS +/* CPU access is not expected to work for this BO */ +#define RADEON_GEM_NO_CPU_ACCESS (1 << 4) #endif static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr, @@ -510,6 +514,8 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr, args.flags |= RADEON_GEM_GTT_WC; if (rdesc->flags & RADEON_FLAG_CPU_ACCESS) args.flags |= RADEON_GEM_CPU_ACCESS; + if (rdesc->flags & RADEON_FLAG_NO_CPU_ACCESS) + args.flags |= RADEON_GEM_NO_CPU_ACCESS; if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE, &args, sizeof(args))) { diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h b/src/gallium/winsys/radeon/drm/radeon_winsys.h index 69bf6ed..18fefbe 100644 --- a/src/gallium/winsys/radeon/drm/radeon_winsys.h +++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h @@ -66,8 +66,9 @@ enum radeon_bo_domain { /* bitfield */ }; enum radeon_bo_flag { /* bitfield */ - RADEON_FLAG_GTT_WC = (1 << 0), - RADEON_FLAG_CPU_ACCESS = (1 << 1), + RADEON_FLAG_GTT_WC = (1 << 0), + RADEON_FLAG_CPU_ACCESS = (1 << 1), + RADEON_FLAG_NO_CPU_ACCESS = (1 << 2), }; enum radeon_bo_usage { /* bitfield */ |