diff options
| author | Matt Turner <mattst88@gmail.com> | 2015-10-26 04:35:14 -0700 |
|---|---|---|
| committer | Matt Turner <mattst88@gmail.com> | 2015-11-13 11:27:50 -0800 |
| commit | 7638e75cf99263c1ee8e31c6cc5a319feec2c943 (patch) | |
| tree | bc5f731f804f538b54d1a5fe92dfe0c47032062c /src | |
| parent | 3048053908310eaf082058e5be34ae902e1fc02c (diff) | |
| download | external_mesa3d-7638e75cf99263c1ee8e31c6cc5a319feec2c943.zip external_mesa3d-7638e75cf99263c1ee8e31c6cc5a319feec2c943.tar.gz external_mesa3d-7638e75cf99263c1ee8e31c6cc5a319feec2c943.tar.bz2 | |
i965: Use brw_reg's nr field to store register number.
In addition to combining another field, we get replace silliness like
"reg.reg" with something that actually makes sense, "reg.nr"; and no one
will ever wonder again why dst.reg isn't a dst_reg.
Moving the now 16-bit nr field to a 16-bit boundary decreases code size
by about 3k.
Reviewed-by: Emil Velikov <emil.velikov@collabora.co.uk>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Diffstat (limited to 'src')
25 files changed, 276 insertions, 290 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index f589e6e..3ea97f2 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -307,7 +307,7 @@ fs_inst::is_copy_payload(const brw::simple_allocator &grf_alloc) const if (reg.file != GRF || reg.reg_offset != 0 || reg.stride == 0) return false; - if (grf_alloc.sizes[reg.reg] != this->regs_written) + if (grf_alloc.sizes[reg.nr] != this->regs_written) return false; for (int i = 0; i < this->sources; i++) { @@ -424,7 +424,6 @@ fs_reg::fs_reg(struct brw_reg reg) : backend_reg(reg) { this->file = HW_REG; - this->reg = 0; this->reg_offset = 0; this->subreg_offset = 0; this->reladdr = NULL; @@ -435,7 +434,7 @@ bool fs_reg::equals(const fs_reg &r) const { return (file == r.file && - reg == r.reg && + nr == r.nr && reg_offset == r.reg_offset && subreg_offset == r.subreg_offset && type == r.type && @@ -959,20 +958,20 @@ fs_visitor::vgrf(const glsl_type *const type) brw_type_for_base_type(type)); } -fs_reg::fs_reg(enum register_file file, int reg) +fs_reg::fs_reg(enum register_file file, int nr) { init(); this->file = file; - this->reg = reg; + this->nr = nr; this->type = BRW_REGISTER_TYPE_F; this->stride = (file == UNIFORM ? 0 : 1); } -fs_reg::fs_reg(enum register_file file, int reg, enum brw_reg_type type) +fs_reg::fs_reg(enum register_file file, int nr, enum brw_reg_type type) { init(); this->file = file; - this->reg = reg; + this->nr = nr; this->type = type; this->stride = (file == UNIFORM ? 0 : 1); } @@ -1456,7 +1455,7 @@ fs_visitor::assign_curb_setup() foreach_block_and_inst(block, fs_inst, inst, cfg) { for (unsigned int i = 0; i < inst->sources; i++) { if (inst->src[i].file == UNIFORM) { - int uniform_nr = inst->src[i].reg + inst->src[i].reg_offset; + int uniform_nr = inst->src[i].nr + inst->src[i].reg_offset; int constant_nr; if (uniform_nr >= 0 && uniform_nr < (int) uniforms) { constant_nr = push_constant_loc[uniform_nr]; @@ -1612,7 +1611,7 @@ fs_visitor::convert_attr_sources_to_hw_regs(fs_inst *inst) if (inst->src[i].file == ATTR) { int grf = payload.num_regs + prog_data->curb_read_length + - inst->src[i].reg + + inst->src[i].nr + inst->src[i].reg_offset; struct brw_reg reg = @@ -1726,15 +1725,15 @@ fs_visitor::split_virtual_grfs() /* Mark all used registers as fully splittable */ foreach_block_and_inst(block, fs_inst, inst, cfg) { if (inst->dst.file == GRF) { - int reg = vgrf_to_reg[inst->dst.reg]; - for (unsigned j = 1; j < this->alloc.sizes[inst->dst.reg]; j++) + int reg = vgrf_to_reg[inst->dst.nr]; + for (unsigned j = 1; j < this->alloc.sizes[inst->dst.nr]; j++) split_points[reg + j] = true; } for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF) { - int reg = vgrf_to_reg[inst->src[i].reg]; - for (unsigned j = 1; j < this->alloc.sizes[inst->src[i].reg]; j++) + int reg = vgrf_to_reg[inst->src[i].nr]; + for (unsigned j = 1; j < this->alloc.sizes[inst->src[i].nr]; j++) split_points[reg + j] = true; } } @@ -1742,13 +1741,13 @@ fs_visitor::split_virtual_grfs() foreach_block_and_inst(block, fs_inst, inst, cfg) { if (inst->dst.file == GRF) { - int reg = vgrf_to_reg[inst->dst.reg] + inst->dst.reg_offset; + int reg = vgrf_to_reg[inst->dst.nr] + inst->dst.reg_offset; for (int j = 1; j < inst->regs_written; j++) split_points[reg + j] = false; } for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF) { - int reg = vgrf_to_reg[inst->src[i].reg] + inst->src[i].reg_offset; + int reg = vgrf_to_reg[inst->src[i].nr] + inst->src[i].reg_offset; for (int j = 1; j < inst->regs_read(i); j++) split_points[reg + j] = false; } @@ -1795,15 +1794,15 @@ fs_visitor::split_virtual_grfs() foreach_block_and_inst(block, fs_inst, inst, cfg) { if (inst->dst.file == GRF) { - reg = vgrf_to_reg[inst->dst.reg] + inst->dst.reg_offset; - inst->dst.reg = new_virtual_grf[reg]; + reg = vgrf_to_reg[inst->dst.nr] + inst->dst.reg_offset; + inst->dst.nr = new_virtual_grf[reg]; inst->dst.reg_offset = new_reg_offset[reg]; assert((unsigned)new_reg_offset[reg] < alloc.sizes[new_virtual_grf[reg]]); } for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF) { - reg = vgrf_to_reg[inst->src[i].reg] + inst->src[i].reg_offset; - inst->src[i].reg = new_virtual_grf[reg]; + reg = vgrf_to_reg[inst->src[i].nr] + inst->src[i].reg_offset; + inst->src[i].nr = new_virtual_grf[reg]; inst->src[i].reg_offset = new_reg_offset[reg]; assert((unsigned)new_reg_offset[reg] < alloc.sizes[new_virtual_grf[reg]]); } @@ -1831,11 +1830,11 @@ fs_visitor::compact_virtual_grfs() /* Mark which virtual GRFs are used. */ foreach_block_and_inst(block, const fs_inst, inst, cfg) { if (inst->dst.file == GRF) - remap_table[inst->dst.reg] = 0; + remap_table[inst->dst.nr] = 0; for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF) - remap_table[inst->src[i].reg] = 0; + remap_table[inst->src[i].nr] = 0; } } @@ -1860,11 +1859,11 @@ fs_visitor::compact_virtual_grfs() /* Patch all the instructions to use the newly renumbered registers */ foreach_block_and_inst(block, fs_inst, inst, cfg) { if (inst->dst.file == GRF) - inst->dst.reg = remap_table[inst->dst.reg]; + inst->dst.nr = remap_table[inst->dst.nr]; for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF) - inst->src[i].reg = remap_table[inst->src[i].reg]; + inst->src[i].nr = remap_table[inst->src[i].nr]; } } @@ -1874,8 +1873,8 @@ fs_visitor::compact_virtual_grfs() */ for (unsigned i = 0; i < ARRAY_SIZE(delta_xy); i++) { if (delta_xy[i].file == GRF) { - if (remap_table[delta_xy[i].reg] != -1) { - delta_xy[i].reg = remap_table[delta_xy[i].reg]; + if (remap_table[delta_xy[i].nr] != -1) { + delta_xy[i].nr = remap_table[delta_xy[i].nr]; } else { delta_xy[i].file = BAD_FILE; } @@ -1927,7 +1926,7 @@ fs_visitor::assign_constant_locations() continue; if (inst->src[i].reladdr) { - int uniform = inst->src[i].reg; + int uniform = inst->src[i].nr; /* If this array isn't already present in the pull constant buffer, * add it. @@ -1939,7 +1938,7 @@ fs_visitor::assign_constant_locations() } } else { /* Mark the the one accessed uniform as live */ - int constant_nr = inst->src[i].reg + inst->src[i].reg_offset; + int constant_nr = inst->src[i].nr + inst->src[i].reg_offset; if (constant_nr >= 0 && constant_nr < (int) uniforms) is_live[constant_nr] = true; } @@ -2015,7 +2014,7 @@ fs_visitor::demote_pull_constants() continue; int pull_index; - unsigned location = inst->src[i].reg + inst->src[i].reg_offset; + unsigned location = inst->src[i].nr + inst->src[i].reg_offset; if (location >= uniforms) /* Out of bounds access */ pull_index = -1; else @@ -2050,7 +2049,7 @@ fs_visitor::demote_pull_constants() /* Rewrite the instruction to use the temporary VGRF. */ inst->src[i].file = GRF; - inst->src[i].reg = dst.reg; + inst->src[i].nr = dst.nr; inst->src[i].reg_offset = 0; } } @@ -2461,30 +2460,30 @@ fs_visitor::opt_register_renaming() /* Rewrite instruction sources. */ for (int i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF && - remap[inst->src[i].reg] != -1 && - remap[inst->src[i].reg] != inst->src[i].reg) { - inst->src[i].reg = remap[inst->src[i].reg]; + remap[inst->src[i].nr] != -1 && + remap[inst->src[i].nr] != inst->src[i].nr) { + inst->src[i].nr = remap[inst->src[i].nr]; progress = true; } } - const int dst = inst->dst.reg; + const int dst = inst->dst.nr; if (depth == 0 && inst->dst.file == GRF && - alloc.sizes[inst->dst.reg] == inst->exec_size / 8 && + alloc.sizes[inst->dst.nr] == inst->exec_size / 8 && !inst->is_partial_write()) { if (remap[dst] == -1) { remap[dst] = dst; } else { remap[dst] = alloc.allocate(inst->exec_size / 8); - inst->dst.reg = remap[dst]; + inst->dst.nr = remap[dst]; progress = true; } } else if (inst->dst.file == GRF && remap[dst] != -1 && remap[dst] != dst) { - inst->dst.reg = remap[dst]; + inst->dst.nr = remap[dst]; progress = true; } } @@ -2493,8 +2492,8 @@ fs_visitor::opt_register_renaming() invalidate_live_intervals(); for (unsigned i = 0; i < ARRAY_SIZE(delta_xy); i++) { - if (delta_xy[i].file == GRF && remap[delta_xy[i].reg] != -1) { - delta_xy[i].reg = remap[delta_xy[i].reg]; + if (delta_xy[i].file == GRF && remap[delta_xy[i].nr] != -1) { + delta_xy[i].nr = remap[delta_xy[i].nr]; } } } @@ -2571,9 +2570,9 @@ fs_visitor::compute_to_mrf() /* Work out which hardware MRF registers are written by this * instruction. */ - int mrf_low = inst->dst.reg & ~BRW_MRF_COMPR4; + int mrf_low = inst->dst.nr & ~BRW_MRF_COMPR4; int mrf_high; - if (inst->dst.reg & BRW_MRF_COMPR4) { + if (inst->dst.nr & BRW_MRF_COMPR4) { mrf_high = mrf_low + 4; } else if (inst->exec_size == 16) { mrf_high = mrf_low + 1; @@ -2584,7 +2583,7 @@ fs_visitor::compute_to_mrf() /* Can't compute-to-MRF this GRF if someone else was going to * read it later. */ - if (this->virtual_grf_end[inst->src[0].reg] > ip) + if (this->virtual_grf_end[inst->src[0].nr] > ip) continue; /* Found a move of a GRF to a MRF. Let's see if we can go @@ -2592,7 +2591,7 @@ fs_visitor::compute_to_mrf() */ foreach_inst_in_block_reverse_starting_from(fs_inst, scan_inst, inst) { if (scan_inst->dst.file == GRF && - scan_inst->dst.reg == inst->src[0].reg) { + scan_inst->dst.nr == inst->src[0].nr) { /* Found the last thing to write our reg we want to turn * into a compute-to-MRF. */ @@ -2627,7 +2626,7 @@ fs_visitor::compute_to_mrf() if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) { /* Found the creator of our MRF's source value. */ scan_inst->dst.file = MRF; - scan_inst->dst.reg = inst->dst.reg; + scan_inst->dst.nr = inst->dst.nr; scan_inst->saturate |= inst->saturate; inst->remove(block); progress = true; @@ -2648,7 +2647,7 @@ fs_visitor::compute_to_mrf() bool interfered = false; for (int i = 0; i < scan_inst->sources; i++) { if (scan_inst->src[i].file == GRF && - scan_inst->src[i].reg == inst->src[0].reg && + scan_inst->src[i].nr == inst->src[0].nr && scan_inst->src[i].reg_offset == inst->src[0].reg_offset) { interfered = true; } @@ -2660,10 +2659,10 @@ fs_visitor::compute_to_mrf() /* If somebody else writes our MRF here, we can't * compute-to-MRF before that. */ - int scan_mrf_low = scan_inst->dst.reg & ~BRW_MRF_COMPR4; + int scan_mrf_low = scan_inst->dst.nr & ~BRW_MRF_COMPR4; int scan_mrf_high; - if (scan_inst->dst.reg & BRW_MRF_COMPR4) { + if (scan_inst->dst.nr & BRW_MRF_COMPR4) { scan_mrf_high = scan_mrf_low + 4; } else if (scan_inst->exec_size == 16) { scan_mrf_high = scan_mrf_low + 1; @@ -2819,7 +2818,7 @@ fs_visitor::remove_duplicate_mrf_writes() if (inst->opcode == BRW_OPCODE_MOV && inst->dst.file == MRF) { - fs_inst *prev_inst = last_mrf_move[inst->dst.reg]; + fs_inst *prev_inst = last_mrf_move[inst->dst.nr]; if (prev_inst && inst->equals(prev_inst)) { inst->remove(block); progress = true; @@ -2829,7 +2828,7 @@ fs_visitor::remove_duplicate_mrf_writes() /* Clear out the last-write records for MRFs that were overwritten. */ if (inst->dst.file == MRF) { - last_mrf_move[inst->dst.reg] = NULL; + last_mrf_move[inst->dst.nr] = NULL; } if (inst->mlen > 0 && inst->base_mrf != -1) { @@ -2845,7 +2844,7 @@ fs_visitor::remove_duplicate_mrf_writes() if (inst->dst.file == GRF) { for (unsigned int i = 0; i < ARRAY_SIZE(last_mrf_move); i++) { if (last_mrf_move[i] && - last_mrf_move[i]->src[0].reg == inst->dst.reg) { + last_mrf_move[i]->src[0].nr == inst->dst.nr) { last_mrf_move[i] = NULL; } } @@ -2855,7 +2854,7 @@ fs_visitor::remove_duplicate_mrf_writes() inst->dst.file == MRF && inst->src[0].file == GRF && !inst->is_partial_write()) { - last_mrf_move[inst->dst.reg] = inst; + last_mrf_move[inst->dst.nr] = inst; } } @@ -2872,7 +2871,7 @@ clear_deps_for_inst_src(fs_inst *inst, bool *deps, int first_grf, int grf_len) for (int i = 0; i < inst->sources; i++) { int grf; if (inst->src[i].file == GRF) { - grf = inst->src[i].reg; + grf = inst->src[i].nr; } else if (inst->src[i].file == HW_REG && inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) { grf = inst->src[i].nr; @@ -2910,7 +2909,7 @@ fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t *block, fs_inst *inst) { int write_len = inst->regs_written; - int first_write_grf = inst->dst.reg; + int first_write_grf = inst->dst.nr; bool needs_dep[BRW_MAX_MRF(devinfo->gen)]; assert(write_len < (int)sizeof(needs_dep) - 1); @@ -2943,7 +2942,7 @@ fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t *block, */ if (scan_inst->dst.file == GRF) { for (int i = 0; i < scan_inst->regs_written; i++) { - int reg = scan_inst->dst.reg + i; + int reg = scan_inst->dst.nr + i; if (reg >= first_write_grf && reg < first_write_grf + write_len && @@ -2981,7 +2980,7 @@ void fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t *block, fs_inst *inst) { int write_len = inst->regs_written; - int first_write_grf = inst->dst.reg; + int first_write_grf = inst->dst.nr; bool needs_dep[BRW_MAX_MRF(devinfo->gen)]; assert(write_len < (int)sizeof(needs_dep) - 1); @@ -3008,12 +3007,12 @@ fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t *block, fs_ins * result of a SEND, which has massive latency. */ if (scan_inst->dst.file == GRF && - scan_inst->dst.reg >= first_write_grf && - scan_inst->dst.reg < first_write_grf + write_len && - needs_dep[scan_inst->dst.reg - first_write_grf]) { + scan_inst->dst.nr >= first_write_grf && + scan_inst->dst.nr < first_write_grf + write_len && + needs_dep[scan_inst->dst.nr - first_write_grf]) { DEP_RESOLVE_MOV(fs_builder(this, block, scan_inst), - scan_inst->dst.reg); - needs_dep[scan_inst->dst.reg - first_write_grf] = false; + scan_inst->dst.nr); + needs_dep[scan_inst->dst.nr - first_write_grf] = false; } /* Continue the loop only if we haven't resolved all the dependencies */ @@ -3145,7 +3144,7 @@ fs_visitor::lower_load_payload() /* Get rid of COMPR4. We'll add it back in if we need it */ if (dst.file == MRF) - dst.reg = dst.reg & ~BRW_MRF_COMPR4; + dst.nr = dst.nr & ~BRW_MRF_COMPR4; const fs_builder ibld(this, block, inst); const fs_builder hbld = ibld.exec_all().group(8, 0); @@ -3159,7 +3158,7 @@ fs_visitor::lower_load_payload() dst = offset(dst, hbld, 1); } - if (inst->dst.file == MRF && (inst->dst.reg & BRW_MRF_COMPR4) && + if (inst->dst.file == MRF && (inst->dst.nr & BRW_MRF_COMPR4) && inst->exec_size > 8) { /* In this case, the payload portion of the LOAD_PAYLOAD isn't * a straightforward copy. Instead, the result of the @@ -3183,18 +3182,18 @@ fs_visitor::lower_load_payload() if (inst->src[i].file != BAD_FILE) { if (devinfo->has_compr4) { fs_reg compr4_dst = retype(dst, inst->src[i].type); - compr4_dst.reg |= BRW_MRF_COMPR4; + compr4_dst.nr |= BRW_MRF_COMPR4; ibld.MOV(compr4_dst, inst->src[i]); } else { /* Platform doesn't have COMPR4. We have to fake it */ fs_reg mov_dst = retype(dst, inst->src[i].type); ibld.half(0).MOV(mov_dst, half(inst->src[i], 0)); - mov_dst.reg += 4; + mov_dst.nr += 4; ibld.half(1).MOV(mov_dst, half(inst->src[i], 1)); } } - dst.reg++; + dst.nr++; } /* The loop above only ever incremented us through the first set @@ -3202,7 +3201,7 @@ fs_visitor::lower_load_payload() * actually wrote to the first 8 registers, so we need to take * that into account now. */ - dst.reg += 4; + dst.nr += 4; /* The COMPR4 code took care of the first 4 sources. We'll let * the regular path handle any remaining sources. Yes, we are @@ -3588,7 +3587,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, /* Send from the GRF */ fs_reg payload = fs_reg(GRF, -1, BRW_REGISTER_TYPE_F); load = bld.LOAD_PAYLOAD(payload, sources, length, payload_header_size); - payload.reg = bld.shader->alloc.allocate(load->regs_written); + payload.nr = bld.shader->alloc.allocate(load->regs_written); load->dst = payload; inst->src[0] = payload; @@ -3603,7 +3602,7 @@ lower_fb_write_logical_send(const fs_builder &bld, fs_inst *inst, * will do this for us if we just give it a COMPR4 destination. */ if (devinfo->gen < 6 && bld.dispatch_width() == 16) - load->dst.reg |= BRW_MRF_COMPR4; + load->dst.nr |= BRW_MRF_COMPR4; inst->resize_sources(0); inst->base_mrf = 1; @@ -3713,8 +3712,8 @@ lower_sampler_logical_send_gen4(const fs_builder &bld, fs_inst *inst, opcode op, inst->src[0] = reg_undef; inst->src[1] = sampler; inst->resize_sources(2); - inst->base_mrf = msg_begin.reg; - inst->mlen = msg_end.reg - msg_begin.reg; + inst->base_mrf = msg_begin.nr; + inst->mlen = msg_end.nr - msg_begin.nr; inst->header_size = 1; } @@ -3738,7 +3737,7 @@ lower_sampler_logical_send_gen5(const fs_builder &bld, fs_inst *inst, opcode op, * go headerless. */ header_size = 1; - message.reg--; + message.nr--; } for (unsigned i = 0; i < coord_components; i++) { @@ -3808,8 +3807,8 @@ lower_sampler_logical_send_gen5(const fs_builder &bld, fs_inst *inst, opcode op, inst->src[0] = reg_undef; inst->src[1] = sampler; inst->resize_sources(2); - inst->base_mrf = message.reg; - inst->mlen = msg_end.reg - message.reg; + inst->base_mrf = message.nr; + inst->mlen = msg_end.nr - message.nr; inst->header_size = header_size; /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */ @@ -4608,23 +4607,23 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) switch (inst->dst.file) { case GRF: - fprintf(file, "vgrf%d", inst->dst.reg); - if (alloc.sizes[inst->dst.reg] != inst->regs_written || + fprintf(file, "vgrf%d", inst->dst.nr); + if (alloc.sizes[inst->dst.nr] != inst->regs_written || inst->dst.subreg_offset) fprintf(file, "+%d.%d", inst->dst.reg_offset, inst->dst.subreg_offset); break; case MRF: - fprintf(file, "m%d", inst->dst.reg); + fprintf(file, "m%d", inst->dst.nr); break; case BAD_FILE: fprintf(file, "(null)"); break; case UNIFORM: - fprintf(file, "***u%d***", inst->dst.reg + inst->dst.reg_offset); + fprintf(file, "***u%d***", inst->dst.nr + inst->dst.reg_offset); break; case ATTR: - fprintf(file, "***attr%d***", inst->dst.reg + inst->dst.reg_offset); + fprintf(file, "***attr%d***", inst->dst.nr + inst->dst.reg_offset); break; case HW_REG: if (inst->dst.brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE) { @@ -4665,20 +4664,20 @@ fs_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) fprintf(file, "|"); switch (inst->src[i].file) { case GRF: - fprintf(file, "vgrf%d", inst->src[i].reg); - if (alloc.sizes[inst->src[i].reg] != (unsigned)inst->regs_read(i) || + fprintf(file, "vgrf%d", inst->src[i].nr); + if (alloc.sizes[inst->src[i].nr] != (unsigned)inst->regs_read(i) || inst->src[i].subreg_offset) fprintf(file, "+%d.%d", inst->src[i].reg_offset, inst->src[i].subreg_offset); break; case MRF: - fprintf(file, "***m%d***", inst->src[i].reg); + fprintf(file, "***m%d***", inst->src[i].nr); break; case ATTR: - fprintf(file, "attr%d+%d", inst->src[i].reg, inst->src[i].reg_offset); + fprintf(file, "attr%d+%d", inst->src[i].nr, inst->src[i].reg_offset); break; case UNIFORM: - fprintf(file, "u%d", inst->src[i].reg + inst->src[i].reg_offset); + fprintf(file, "u%d", inst->src[i].nr + inst->src[i].reg_offset); if (inst->src[i].reladdr) { fprintf(file, "+reladdr"); } else if (inst->src[i].subreg_offset) { diff --git a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp index 234bbec..127cee4 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp @@ -121,7 +121,7 @@ struct imm { * constant value. */ uint8_t subreg_offset; - uint16_t reg; + uint16_t nr; /** The number of coissuable instructions using this immediate. */ uint16_t uses_by_coissue; @@ -280,12 +280,12 @@ fs_visitor::opt_combine_constants() const fs_builder ibld = bld.at(imm->block, n).exec_all().group(1, 0); ibld.MOV(reg, fs_reg(imm->val)); - imm->reg = reg.reg; + imm->nr = reg.nr; imm->subreg_offset = reg.subreg_offset; reg.subreg_offset += sizeof(float); if ((unsigned)reg.subreg_offset == dispatch_width * sizeof(float)) { - reg.reg = alloc.allocate(dispatch_width / 8); + reg.nr = alloc.allocate(dispatch_width / 8); reg.subreg_offset = 0; } } @@ -296,7 +296,7 @@ fs_visitor::opt_combine_constants() foreach_list_typed(reg_link, link, link, table.imm[i].uses) { fs_reg *reg = link->reg; reg->file = GRF; - reg->reg = table.imm[i].reg; + reg->nr = table.imm[i].nr; reg->subreg_offset = table.imm[i].subreg_offset; reg->stride = 0; reg->negate = signbit(reg->f) != signbit(table.imm[i].val); diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp index 2c966d1..7959413 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp @@ -291,7 +291,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry) return false; assert(entry->dst.file == GRF); - if (inst->src[arg].reg != entry->dst.reg) + if (inst->src[arg].nr != entry->dst.nr) return false; /* Bail if inst is reading a range that isn't contained in the range @@ -380,7 +380,7 @@ fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry) } inst->src[arg].file = entry->src.file; - inst->src[arg].reg = entry->src.reg; + inst->src[arg].nr = entry->src.nr; inst->src[arg].stride *= entry->src.stride; inst->saturate = inst->saturate || entry->saturate; @@ -460,7 +460,7 @@ fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry) continue; assert(entry->dst.file == GRF); - if (inst->src[i].reg != entry->dst.reg) + if (inst->src[i].nr != entry->dst.nr) continue; /* Bail if inst is reading a range that isn't contained in the range @@ -654,7 +654,7 @@ can_propagate_from(fs_inst *inst) return (inst->opcode == BRW_OPCODE_MOV && inst->dst.file == GRF && ((inst->src[0].file == GRF && - (inst->src[0].reg != inst->dst.reg || + (inst->src[0].nr != inst->dst.nr || inst->src[0].reg_offset != inst->dst.reg_offset)) || inst->src[0].file == ATTR || inst->src[0].file == UNIFORM || @@ -678,7 +678,7 @@ fs_visitor::opt_copy_propagate_local(void *copy_prop_ctx, bblock_t *block, if (inst->src[i].file != GRF) continue; - foreach_in_list(acp_entry, entry, &acp[inst->src[i].reg % ACP_HASH_SIZE]) { + foreach_in_list(acp_entry, entry, &acp[inst->src[i].nr % ACP_HASH_SIZE]) { if (try_constant_propagate(inst, entry)) progress = true; @@ -689,7 +689,7 @@ fs_visitor::opt_copy_propagate_local(void *copy_prop_ctx, bblock_t *block, /* kill the destination from the ACP */ if (inst->dst.file == GRF) { - foreach_in_list_safe(acp_entry, entry, &acp[inst->dst.reg % ACP_HASH_SIZE]) { + foreach_in_list_safe(acp_entry, entry, &acp[inst->dst.nr % ACP_HASH_SIZE]) { if (inst->overwrites_reg(entry->dst)) { entry->remove(); } @@ -716,7 +716,7 @@ fs_visitor::opt_copy_propagate_local(void *copy_prop_ctx, bblock_t *block, entry->regs_written = inst->regs_written; entry->opcode = inst->opcode; entry->saturate = inst->saturate; - acp[entry->dst.reg % ACP_HASH_SIZE].push_tail(entry); + acp[entry->dst.nr % ACP_HASH_SIZE].push_tail(entry); } else if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD && inst->dst.file == GRF) { int offset = 0; @@ -731,7 +731,7 @@ fs_visitor::opt_copy_propagate_local(void *copy_prop_ctx, bblock_t *block, entry->regs_written = regs_written; entry->opcode = inst->opcode; if (!entry->dst.equals(inst->src[i])) { - acp[entry->dst.reg % ACP_HASH_SIZE].push_tail(entry); + acp[entry->dst.nr % ACP_HASH_SIZE].push_tail(entry); } else { ralloc_free(entry); } @@ -774,7 +774,7 @@ fs_visitor::opt_copy_propagate() for (int i = 0; i < dataflow.num_acp; i++) { if (BITSET_TEST(dataflow.bd[block->num].livein, i)) { struct acp_entry *entry = dataflow.acp[i]; - in_acp[entry->dst.reg % ACP_HASH_SIZE].push_tail(entry); + in_acp[entry->dst.nr % ACP_HASH_SIZE].push_tail(entry); } } diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp index fbf00d1..08f89d5 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp @@ -320,7 +320,7 @@ fs_visitor::opt_cse_local(bblock_t *block) /* Kill any AEB entries using registers that don't get reused any * more -- a sure sign they'll fail operands_match(). */ - if (src_reg->file == GRF && virtual_grf_end[src_reg->reg] < ip) { + if (src_reg->file == GRF && virtual_grf_end[src_reg->nr] < ip) { entry->remove(); ralloc_free(entry); break; diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 6b6b577..95649d8 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -59,13 +59,13 @@ brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen) switch (reg->file) { case MRF: - assert((reg->reg & ~(1 << 7)) < BRW_MAX_MRF(gen)); + assert((reg->nr & ~(1 << 7)) < BRW_MAX_MRF(gen)); /* Fallthrough */ case GRF: if (reg->stride == 0) { - brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0); + brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0); } else if (inst->exec_size < 8) { - brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0); + brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0); brw_reg = stride(brw_reg, inst->exec_size * reg->stride, inst->exec_size, reg->stride); } else { @@ -78,7 +78,7 @@ brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen) * So, for registers with width > 8, we have to use a width of 8 * and trust the compression state to sort out the exec size. */ - brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0); + brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0); brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride); } diff --git a/src/mesa/drivers/dri/i965/brw_fs_live_variables.h b/src/mesa/drivers/dri/i965/brw_fs_live_variables.h index c745706..96cadea 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_live_variables.h +++ b/src/mesa/drivers/dri/i965/brw_fs_live_variables.h @@ -68,7 +68,7 @@ public: bool vars_interfere(int a, int b); int var_from_reg(const fs_reg ®) const { - return var_from_vgrf[reg.reg] + reg.reg_offset; + return var_from_vgrf[reg.nr] + reg.reg_offset; } /** Map from virtual GRF number to index in block_data arrays. */ diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp index 3e0e0e9..99ccdb1 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp @@ -36,7 +36,7 @@ static void assign_reg(unsigned *reg_hw_locations, fs_reg *reg) { if (reg->file == GRF) { - reg->reg = reg_hw_locations[reg->reg] + reg->reg_offset; + reg->nr = reg_hw_locations[reg->nr] + reg->reg_offset; reg->reg_offset = 0; } } @@ -489,10 +489,10 @@ get_used_mrfs(fs_visitor *v, bool *mrf_used) foreach_block_and_inst(block, fs_inst, inst, v->cfg) { if (inst->dst.file == MRF) { - int reg = inst->dst.reg & ~BRW_MRF_COMPR4; + int reg = inst->dst.nr & ~BRW_MRF_COMPR4; mrf_used[reg] = true; if (reg_width == 2) { - if (inst->dst.reg & BRW_MRF_COMPR4) { + if (inst->dst.nr & BRW_MRF_COMPR4) { mrf_used[reg + 4] = true; } else { mrf_used[reg + 1] = true; @@ -585,7 +585,7 @@ fs_visitor::assign_regs(bool allow_spilling) */ if (compiler->fs_reg_sets[rsi].aligned_pairs_class >= 0 && this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF && - this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg == i) { + this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].nr == i) { c = compiler->fs_reg_sets[rsi].aligned_pairs_class; } @@ -616,7 +616,7 @@ fs_visitor::assign_regs(bool allow_spilling) * highest register that works. */ if (inst->eot) { - int size = alloc.sizes[inst->src[0].reg]; + int size = alloc.sizes[inst->src[0].nr]; int reg = compiler->fs_reg_sets[rsi].class_to_ra_reg_range[size] - 1; /* If something happened to spill, we want to push the EOT send @@ -625,7 +625,7 @@ fs_visitor::assign_regs(bool allow_spilling) */ reg -= BRW_MAX_MRF(devinfo->gen) - first_used_mrf; - ra_set_node_reg(g, inst->src[0].reg, reg); + ra_set_node_reg(g, inst->src[0].nr, reg); break; } } @@ -649,7 +649,7 @@ fs_visitor::assign_regs(bool allow_spilling) for (int i = 0; i < inst->sources; ++i) { if (inst->src[i].file == GRF) { - ra_add_node_interference(g, inst->dst.reg, inst->src[i].reg); + ra_add_node_interference(g, inst->dst.nr, inst->src[i].nr); } } } @@ -787,7 +787,7 @@ fs_visitor::choose_spill_reg(struct ra_graph *g) foreach_block_and_inst(block, fs_inst, inst, cfg) { for (unsigned int i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF) { - spill_costs[inst->src[i].reg] += loop_scale; + spill_costs[inst->src[i].nr] += loop_scale; /* Register spilling logic assumes full-width registers; smeared * registers have a width of 1 so if we try to spill them we'll @@ -797,16 +797,16 @@ fs_visitor::choose_spill_reg(struct ra_graph *g) * register pressure anyhow. */ if (!inst->src[i].is_contiguous()) { - no_spill[inst->src[i].reg] = true; + no_spill[inst->src[i].nr] = true; } } } if (inst->dst.file == GRF) { - spill_costs[inst->dst.reg] += inst->regs_written * loop_scale; + spill_costs[inst->dst.nr] += inst->regs_written * loop_scale; if (!inst->dst.is_contiguous()) { - no_spill[inst->dst.reg] = true; + no_spill[inst->dst.nr] = true; } } @@ -822,13 +822,13 @@ fs_visitor::choose_spill_reg(struct ra_graph *g) case SHADER_OPCODE_GEN4_SCRATCH_WRITE: if (inst->src[0].file == GRF) - no_spill[inst->src[0].reg] = true; + no_spill[inst->src[0].nr] = true; break; case SHADER_OPCODE_GEN4_SCRATCH_READ: case SHADER_OPCODE_GEN7_SCRATCH_READ: if (inst->dst.file == GRF) - no_spill[inst->dst.reg] = true; + no_spill[inst->dst.nr] = true; break; default: @@ -884,13 +884,13 @@ fs_visitor::spill_reg(int spill_reg) foreach_block_and_inst (block, fs_inst, inst, cfg) { for (unsigned int i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF && - inst->src[i].reg == spill_reg) { + inst->src[i].nr == spill_reg) { int regs_read = inst->regs_read(i); int subset_spill_offset = (spill_offset + REG_SIZE * inst->src[i].reg_offset); fs_reg unspill_dst(GRF, alloc.allocate(regs_read)); - inst->src[i].reg = unspill_dst.reg; + inst->src[i].nr = unspill_dst.nr; inst->src[i].reg_offset = 0; emit_unspill(block, inst, unspill_dst, subset_spill_offset, @@ -899,12 +899,12 @@ fs_visitor::spill_reg(int spill_reg) } if (inst->dst.file == GRF && - inst->dst.reg == spill_reg) { + inst->dst.nr == spill_reg) { int subset_spill_offset = (spill_offset + REG_SIZE * inst->dst.reg_offset); fs_reg spill_src(GRF, alloc.allocate(inst->regs_written)); - inst->dst.reg = spill_src.reg; + inst->dst.nr = spill_src.nr; inst->dst.reg_offset = 0; /* If we're immediately spilling the register, we should not use diff --git a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp index 34f8715..ce1d66e 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp @@ -79,8 +79,8 @@ is_coalesce_candidate(const fs_visitor *v, const fs_inst *inst) return false; } - if (v->alloc.sizes[inst->src[0].reg] > - v->alloc.sizes[inst->dst.reg]) + if (v->alloc.sizes[inst->src[0].nr] > + v->alloc.sizes[inst->dst.nr]) return false; if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { @@ -170,19 +170,19 @@ fs_visitor::register_coalesce() continue; } - if (src_reg != inst->src[0].reg) { - src_reg = inst->src[0].reg; + if (src_reg != inst->src[0].nr) { + src_reg = inst->src[0].nr; - src_size = alloc.sizes[inst->src[0].reg]; + src_size = alloc.sizes[inst->src[0].nr]; assert(src_size <= MAX_VGRF_SIZE); channels_remaining = src_size; memset(mov, 0, sizeof(mov)); - dst_reg = inst->dst.reg; + dst_reg = inst->dst.nr; } - if (dst_reg != inst->dst.reg) + if (dst_reg != inst->dst.nr) continue; if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) { @@ -251,16 +251,16 @@ fs_visitor::register_coalesce() foreach_block_and_inst(block, fs_inst, scan_inst, cfg) { if (scan_inst->dst.file == GRF && - scan_inst->dst.reg == src_reg) { - scan_inst->dst.reg = dst_reg; + scan_inst->dst.nr == src_reg) { + scan_inst->dst.nr = dst_reg; scan_inst->dst.reg_offset = dst_reg_offset[scan_inst->dst.reg_offset]; } for (int j = 0; j < scan_inst->sources; j++) { if (scan_inst->src[j].file == GRF && - scan_inst->src[j].reg == src_reg) { - scan_inst->src[j].reg = dst_reg; + scan_inst->src[j].nr == src_reg) { + scan_inst->src[j].nr = dst_reg; scan_inst->src[j].reg_offset = dst_reg_offset[scan_inst->src[j].reg_offset]; } diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp index 862e324..0c48dcd 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp @@ -91,7 +91,7 @@ opt_saturate_propagation_local(fs_visitor *v, bblock_t *block) } for (int i = 0; i < scan_inst->sources; i++) { if (scan_inst->src[i].file == GRF && - scan_inst->src[i].reg == inst->src[0].reg && + scan_inst->src[i].nr == inst->src[0].nr && scan_inst->src[i].reg_offset == inst->src[0].reg_offset) { if (scan_inst->opcode != BRW_OPCODE_MOV || !scan_inst->saturate || diff --git a/src/mesa/drivers/dri/i965/brw_fs_validate.cpp b/src/mesa/drivers/dri/i965/brw_fs_validate.cpp index 814c551..a79c343 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_validate.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_validate.cpp @@ -44,13 +44,13 @@ fs_visitor::validate() foreach_block_and_inst (block, fs_inst, inst, cfg) { if (inst->dst.file == GRF) { fsv_assert(inst->dst.reg_offset + inst->regs_written <= - alloc.sizes[inst->dst.reg]); + alloc.sizes[inst->dst.nr]); } for (unsigned i = 0; i < inst->sources; i++) { if (inst->src[i].file == GRF) { fsv_assert(inst->src[i].reg_offset + inst->regs_read(i) <= - (int)alloc.sizes[inst->src[i].reg]); + (int)alloc.sizes[inst->src[i].nr]); } } } diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp index 66a0c90..da7e9ca 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp @@ -876,7 +876,7 @@ void fs_visitor::compute_clip_distance(gl_clip_plane *clip_planes) abld.MUL(output, outputs[clip_vertex], u); for (int j = 1; j < 4; j++) { - u.reg = userplane[i].reg + j; + u.nr = userplane[i].nr + j; abld.MAD(output, output, offset(outputs[clip_vertex], bld, j), u); } } diff --git a/src/mesa/drivers/dri/i965/brw_ir_fs.h b/src/mesa/drivers/dri/i965/brw_ir_fs.h index 1f2931a..9309ba5 100644 --- a/src/mesa/drivers/dri/i965/brw_ir_fs.h +++ b/src/mesa/drivers/dri/i965/brw_ir_fs.h @@ -42,8 +42,8 @@ public: explicit fs_reg(uint8_t vf[4]); explicit fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3); fs_reg(struct brw_reg reg); - fs_reg(enum register_file file, int reg); - fs_reg(enum register_file file, int reg, enum brw_reg_type type); + fs_reg(enum register_file file, int nr); + fs_reg(enum register_file file, int nr, enum brw_reg_type type); bool equals(const fs_reg &r) const; bool is_contiguous() const; @@ -95,7 +95,7 @@ byte_offset(fs_reg reg, unsigned delta) reg.reg_offset += delta / 32; break; case MRF: - reg.reg += delta / 32; + reg.nr += delta / 32; break; case IMM: case HW_REG: diff --git a/src/mesa/drivers/dri/i965/brw_ir_vec4.h b/src/mesa/drivers/dri/i965/brw_ir_vec4.h index a19a262..d3f0d61 100644 --- a/src/mesa/drivers/dri/i965/brw_ir_vec4.h +++ b/src/mesa/drivers/dri/i965/brw_ir_vec4.h @@ -39,7 +39,7 @@ public: void init(); - src_reg(register_file file, int reg, const glsl_type *type); + src_reg(register_file file, int nr, const glsl_type *type); src_reg(); src_reg(float f); src_reg(uint32_t u); @@ -107,10 +107,10 @@ public: void init(); dst_reg(); - dst_reg(register_file file, int reg); - dst_reg(register_file file, int reg, const glsl_type *type, + dst_reg(register_file file, int nr); + dst_reg(register_file file, int nr, const glsl_type *type, unsigned writemask); - dst_reg(register_file file, int reg, brw_reg_type type, + dst_reg(register_file file, int nr, brw_reg_type type, unsigned writemask); dst_reg(struct brw_reg reg); dst_reg(class vec4_visitor *v, const struct glsl_type *type); diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h index 8fc2fee..a2f4155 100644 --- a/src/mesa/drivers/dri/i965/brw_reg.h +++ b/src/mesa/drivers/dri/i965/brw_reg.h @@ -233,12 +233,12 @@ const char *brw_reg_type_letters(unsigned brw_reg_type); struct brw_reg { enum brw_reg_type type:4; enum brw_reg_file file:2; - unsigned nr:8; - unsigned subnr:5; /* :1 in align16 */ unsigned negate:1; /* source only */ unsigned abs:1; /* source only */ unsigned address_mode:1; /* relative addressing, hopefully! */ - unsigned pad0:10; + unsigned pad0:2; + unsigned subnr:5; /* :1 in align16 */ + unsigned nr:16; union { struct { @@ -353,12 +353,12 @@ brw_reg(enum brw_reg_file file, reg.type = type; reg.file = file; - reg.nr = nr; - reg.subnr = subnr * type_sz(type); reg.negate = negate; reg.abs = abs; reg.address_mode = BRW_ADDRESS_DIRECT; reg.pad0 = 0; + reg.subnr = subnr * type_sz(type); + reg.nr = nr; /* Could do better: If the reg is r5.3<0;1,0>, we probably want to * set swizzle and writemask to W, as the lower bits of subnr will diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp index 521d04e..2f92595 100644 --- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp +++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp @@ -584,7 +584,7 @@ fs_instruction_scheduler::count_reads_remaining(backend_instruction *be) continue; if (inst->src[i].file == GRF) { - reads_remaining[inst->src[i].reg]++; + reads_remaining[inst->src[i].nr]++; } else if (inst->src[i].file == HW_REG && inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE) { if (inst->src[i].nr >= hw_reg_count) @@ -661,7 +661,7 @@ fs_instruction_scheduler::update_register_pressure(backend_instruction *be) return; if (inst->dst.file == GRF) { - written[inst->dst.reg] = true; + written[inst->dst.nr] = true; } for (int i = 0; i < inst->sources; i++) { @@ -669,7 +669,7 @@ fs_instruction_scheduler::update_register_pressure(backend_instruction *be) continue; if (inst->src[i].file == GRF) { - reads_remaining[inst->src[i].reg]--; + reads_remaining[inst->src[i].nr]--; } else if (inst->src[i].file == HW_REG && inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE && inst->src[i].nr < hw_reg_count) { @@ -686,9 +686,9 @@ fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be) int benefit = 0; if (inst->dst.file == GRF) { - if (!BITSET_TEST(livein[block_idx], inst->dst.reg) && - !written[inst->dst.reg]) - benefit -= v->alloc.sizes[inst->dst.reg]; + if (!BITSET_TEST(livein[block_idx], inst->dst.nr) && + !written[inst->dst.nr]) + benefit -= v->alloc.sizes[inst->dst.nr]; } for (int i = 0; i < inst->sources; i++) { @@ -696,9 +696,9 @@ fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction *be) continue; if (inst->src[i].file == GRF && - !BITSET_TEST(liveout[block_idx], inst->src[i].reg) && - reads_remaining[inst->src[i].reg] == 1) - benefit += v->alloc.sizes[inst->src[i].reg]; + !BITSET_TEST(liveout[block_idx], inst->src[i].nr) && + reads_remaining[inst->src[i].nr] == 1) + benefit += v->alloc.sizes[inst->src[i].nr]; if (inst->src[i].file == HW_REG && inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE && @@ -953,10 +953,10 @@ fs_instruction_scheduler::calculate_deps() if (inst->src[i].file == GRF) { if (post_reg_alloc) { for (int r = 0; r < inst->regs_read(i); r++) - add_dep(last_grf_write[inst->src[i].reg + r], n); + add_dep(last_grf_write[inst->src[i].nr + r], n); } else { for (int r = 0; r < inst->regs_read(i); r++) { - add_dep(last_grf_write[inst->src[i].reg * 16 + inst->src[i].reg_offset + r], n); + add_dep(last_grf_write[inst->src[i].nr * 16 + inst->src[i].reg_offset + r], n); } } } else if (inst->src[i].file == HW_REG && @@ -1002,22 +1002,22 @@ fs_instruction_scheduler::calculate_deps() if (inst->dst.file == GRF) { if (post_reg_alloc) { for (int r = 0; r < inst->regs_written; r++) { - add_dep(last_grf_write[inst->dst.reg + r], n); - last_grf_write[inst->dst.reg + r] = n; + add_dep(last_grf_write[inst->dst.nr + r], n); + last_grf_write[inst->dst.nr + r] = n; } } else { for (int r = 0; r < inst->regs_written; r++) { - add_dep(last_grf_write[inst->dst.reg * 16 + inst->dst.reg_offset + r], n); - last_grf_write[inst->dst.reg * 16 + inst->dst.reg_offset + r] = n; + add_dep(last_grf_write[inst->dst.nr * 16 + inst->dst.reg_offset + r], n); + last_grf_write[inst->dst.nr * 16 + inst->dst.reg_offset + r] = n; } } } else if (inst->dst.file == MRF) { - int reg = inst->dst.reg & ~BRW_MRF_COMPR4; + int reg = inst->dst.nr & ~BRW_MRF_COMPR4; add_dep(last_mrf_write[reg], n); last_mrf_write[reg] = n; if (is_compressed(inst)) { - if (inst->dst.reg & BRW_MRF_COMPR4) + if (inst->dst.nr & BRW_MRF_COMPR4) reg += 4; else reg++; @@ -1079,10 +1079,10 @@ fs_instruction_scheduler::calculate_deps() if (inst->src[i].file == GRF) { if (post_reg_alloc) { for (int r = 0; r < inst->regs_read(i); r++) - add_dep(n, last_grf_write[inst->src[i].reg + r], 0); + add_dep(n, last_grf_write[inst->src[i].nr + r], 0); } else { for (int r = 0; r < inst->regs_read(i); r++) { - add_dep(n, last_grf_write[inst->src[i].reg * 16 + inst->src[i].reg_offset + r], 0); + add_dep(n, last_grf_write[inst->src[i].nr * 16 + inst->src[i].reg_offset + r], 0); } } } else if (inst->src[i].file == HW_REG && @@ -1130,19 +1130,19 @@ fs_instruction_scheduler::calculate_deps() if (inst->dst.file == GRF) { if (post_reg_alloc) { for (int r = 0; r < inst->regs_written; r++) - last_grf_write[inst->dst.reg + r] = n; + last_grf_write[inst->dst.nr + r] = n; } else { for (int r = 0; r < inst->regs_written; r++) { - last_grf_write[inst->dst.reg * 16 + inst->dst.reg_offset + r] = n; + last_grf_write[inst->dst.nr * 16 + inst->dst.reg_offset + r] = n; } } } else if (inst->dst.file == MRF) { - int reg = inst->dst.reg & ~BRW_MRF_COMPR4; + int reg = inst->dst.nr & ~BRW_MRF_COMPR4; last_mrf_write[reg] = n; if (is_compressed(inst)) { - if (inst->dst.reg & BRW_MRF_COMPR4) + if (inst->dst.nr & BRW_MRF_COMPR4) reg += 4; else reg++; @@ -1217,7 +1217,7 @@ vec4_instruction_scheduler::calculate_deps() for (int i = 0; i < 3; i++) { if (inst->src[i].file == GRF) { for (unsigned j = 0; j < inst->regs_read(i); ++j) - add_dep(last_grf_write[inst->src[i].reg + j], n); + add_dep(last_grf_write[inst->src[i].nr + j], n); } else if (inst->src[i].file == HW_REG && (inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE)) { @@ -1260,12 +1260,12 @@ vec4_instruction_scheduler::calculate_deps() /* write-after-write deps. */ if (inst->dst.file == GRF) { for (unsigned j = 0; j < inst->regs_written; ++j) { - add_dep(last_grf_write[inst->dst.reg + j], n); - last_grf_write[inst->dst.reg + j] = n; + add_dep(last_grf_write[inst->dst.nr + j], n); + last_grf_write[inst->dst.nr + j] = n; } } else if (inst->dst.file == MRF) { - add_dep(last_mrf_write[inst->dst.reg], n); - last_mrf_write[inst->dst.reg] = n; + add_dep(last_mrf_write[inst->dst.nr], n); + last_mrf_write[inst->dst.nr] = n; } else if (inst->dst.file == HW_REG && inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) { last_fixed_grf_write = n; @@ -1315,7 +1315,7 @@ vec4_instruction_scheduler::calculate_deps() for (int i = 0; i < 3; i++) { if (inst->src[i].file == GRF) { for (unsigned j = 0; j < inst->regs_read(i); ++j) - add_dep(n, last_grf_write[inst->src[i].reg + j]); + add_dep(n, last_grf_write[inst->src[i].nr + j]); } else if (inst->src[i].file == HW_REG && (inst->src[i].brw_reg::file == BRW_GENERAL_REGISTER_FILE)) { @@ -1356,9 +1356,9 @@ vec4_instruction_scheduler::calculate_deps() */ if (inst->dst.file == GRF) { for (unsigned j = 0; j < inst->regs_written; ++j) - last_grf_write[inst->dst.reg + j] = n; + last_grf_write[inst->dst.nr + j] = n; } else if (inst->dst.file == MRF) { - last_mrf_write[inst->dst.reg] = n; + last_mrf_write[inst->dst.nr] = n; } else if (inst->dst.file == HW_REG && inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) { last_fixed_grf_write = n; diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index ca7db9a..d736d0e 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -751,7 +751,7 @@ bool backend_reg::in_range(const backend_reg &r, unsigned n) const { return (file == r.file && - reg == r.reg && + nr == r.nr && reg_offset >= r.reg_offset && reg_offset < r.reg_offset + n); } diff --git a/src/mesa/drivers/dri/i965/brw_shader.h b/src/mesa/drivers/dri/i965/brw_shader.h index 086ab60..67d623c 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.h +++ b/src/mesa/drivers/dri/i965/brw_shader.h @@ -64,15 +64,6 @@ struct backend_reg : public brw_reg enum register_file file; /**< Register file: GRF, MRF, IMM. */ /** - * Register number. - * - * For GRF, it's a virtual register number until register allocation. - * - * For MRF, it's the hardware register. - */ - uint16_t reg; - - /** * Offset within the virtual register. * * In the scalar backend, this is in units of a float per pixel for pre- diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp index 8c2056b..0570b00 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp @@ -51,12 +51,12 @@ src_reg::init() this->file = BAD_FILE; } -src_reg::src_reg(register_file file, int reg, const glsl_type *type) +src_reg::src_reg(register_file file, int nr, const glsl_type *type) { init(); this->file = file; - this->reg = reg; + this->nr = nr; if (type && (type->is_scalar() || type->is_vector() || type->is_matrix())) this->swizzle = brw_swizzle_for_size(type->vector_elements); else @@ -120,7 +120,6 @@ src_reg::src_reg(struct brw_reg reg) : backend_reg(reg) { this->file = HW_REG; - this->reg = 0; this->reg_offset = 0; this->reladdr = NULL; } @@ -129,7 +128,6 @@ src_reg::src_reg(const dst_reg ®) : backend_reg(static_cast<struct brw_reg>(reg)) { this->file = reg.file; - this->reg = reg.reg; this->reg_offset = reg.reg_offset; this->reladdr = reg.reladdr; this->swizzle = brw_swizzle_for_mask(reg.writemask); @@ -148,32 +146,32 @@ dst_reg::dst_reg() init(); } -dst_reg::dst_reg(register_file file, int reg) +dst_reg::dst_reg(register_file file, int nr) { init(); this->file = file; - this->reg = reg; + this->nr = nr; } -dst_reg::dst_reg(register_file file, int reg, const glsl_type *type, +dst_reg::dst_reg(register_file file, int nr, const glsl_type *type, unsigned writemask) { init(); this->file = file; - this->reg = reg; + this->nr = nr; this->type = brw_type_for_base_type(type); this->writemask = writemask; } -dst_reg::dst_reg(register_file file, int reg, brw_reg_type type, +dst_reg::dst_reg(register_file file, int nr, brw_reg_type type, unsigned writemask) { init(); this->file = file; - this->reg = reg; + this->nr = nr; this->type = type; this->writemask = writemask; } @@ -182,7 +180,6 @@ dst_reg::dst_reg(struct brw_reg reg) : backend_reg(reg) { this->file = HW_REG; - this->reg = 0; this->reg_offset = 0; this->reladdr = NULL; } @@ -191,7 +188,6 @@ dst_reg::dst_reg(const src_reg ®) : backend_reg(static_cast<struct brw_reg>(reg)) { this->file = reg.file; - this->reg = reg.reg; this->reg_offset = reg.reg_offset; this->writemask = brw_mask_for_swizzle(reg.swizzle); this->reladdr = reg.reladdr; @@ -201,7 +197,7 @@ bool dst_reg::equals(const dst_reg &r) const { return (file == r.file && - reg == r.reg && + nr == r.nr && reg_offset == r.reg_offset && type == r.type && negate == r.negate && @@ -346,7 +342,7 @@ bool src_reg::equals(const src_reg &r) const { return (file == r.file && - reg == r.reg && + nr == r.nr && reg_offset == r.reg_offset && type == r.type && negate == r.negate && @@ -372,10 +368,10 @@ vec4_visitor::opt_vector_float() vec4_instruction *imm_inst[4]; foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { - if (last_reg != inst->dst.reg || + if (last_reg != inst->dst.nr || last_reg_offset != inst->dst.reg_offset || last_reg_file != inst->dst.file) { - last_reg = inst->dst.reg; + last_reg = inst->dst.nr; last_reg_offset = inst->dst.reg_offset; last_reg_file = inst->dst.file; remaining_channels = WRITEMASK_XYZW; @@ -497,7 +493,7 @@ vec4_visitor::split_uniform_registers() /* Prior to this, uniforms have been in an array sized according to * the number of vector uniforms present, sparsely filled (so an * aggregate results in reg indices being skipped over). Now we're - * going to cut those aggregates up so each .reg index is one + * going to cut those aggregates up so each .nr index is one * vector. The goal is to make elimination of unused uniform * components easier later. */ @@ -508,7 +504,7 @@ vec4_visitor::split_uniform_registers() assert(!inst->src[i].reladdr); - inst->src[i].reg += inst->src[i].reg_offset; + inst->src[i].nr += inst->src[i].reg_offset; inst->src[i].reg_offset = 0; } } @@ -557,7 +553,7 @@ vec4_visitor::pack_uniform_registers() if (inst->src[i].file != UNIFORM) continue; - int reg = inst->src[i].reg; + int reg = inst->src[i].nr; for (int c = 0; c < 4; c++) { if (!(readmask & (1 << c))) continue; @@ -612,12 +608,12 @@ vec4_visitor::pack_uniform_registers() /* Now, update the instructions for our repacked uniforms. */ foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (int i = 0 ; i < 3; i++) { - int src = inst->src[i].reg; + int src = inst->src[i].nr; if (inst->src[i].file != UNIFORM) continue; - inst->src[i].reg = new_loc[src]; + inst->src[i].nr = new_loc[src]; inst->src[i].swizzle += BRW_SWIZZLE4(new_chan[src], new_chan[src], new_chan[src], new_chan[src]); } @@ -812,10 +808,10 @@ vec4_visitor::move_push_constants_to_pull_constants() foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) { for (int i = 0 ; i < 3; i++) { if (inst->src[i].file != UNIFORM || - pull_constant_loc[inst->src[i].reg] == -1) + pull_constant_loc[inst->src[i].nr] == -1) continue; - int uniform = inst->src[i].reg; + int uniform = inst->src[i].nr; dst_reg temp = dst_reg(this, glsl_type::vec4_type); @@ -823,7 +819,7 @@ vec4_visitor::move_push_constants_to_pull_constants() pull_constant_loc[uniform]); inst->src[i].file = temp.file; - inst->src[i].reg = temp.reg; + inst->src[i].nr = temp.nr; inst->src[i].reg_offset = temp.reg_offset; inst->src[i].reladdr = NULL; } @@ -915,7 +911,7 @@ vec4_visitor::opt_set_dependency_control() * on, don't do dependency control across the read. */ for (int i = 0; i < 3; i++) { - int reg = inst->src[i].reg + inst->src[i].reg_offset; + int reg = inst->src[i].nr + inst->src[i].reg_offset; if (inst->src[i].file == GRF) { last_grf_write[reg] = NULL; } else if (inst->src[i].file == HW_REG) { @@ -934,7 +930,7 @@ vec4_visitor::opt_set_dependency_control() /* Now, see if we can do dependency control for this instruction * against a previous one writing to its destination. */ - int reg = inst->dst.reg + inst->dst.reg_offset; + int reg = inst->dst.nr + inst->dst.reg_offset; if (inst->dst.file == GRF) { if (last_grf_write[reg] && !(inst->dst.writemask & grf_channels_written[reg])) { @@ -957,7 +953,7 @@ vec4_visitor::opt_set_dependency_control() last_mrf_write[reg] = inst; mrf_channels_written[reg] |= inst->dst.writemask; - } else if (inst->dst.reg == HW_REG) { + } else if (inst->dst.nr == HW_REG) { if (inst->dst.brw_reg::file == BRW_GENERAL_REGISTER_FILE) memset(last_grf_write, 0, sizeof(last_grf_write)); if (inst->dst.brw_reg::file == BRW_MESSAGE_REGISTER_FILE) @@ -1058,7 +1054,7 @@ vec4_visitor::opt_register_coalesce() /* Remove no-op MOVs */ if (inst->dst.file == inst->src[0].file && - inst->dst.reg == inst->src[0].reg && + inst->dst.nr == inst->src[0].nr && inst->dst.reg_offset == inst->src[0].reg_offset) { bool is_nop_mov = true; @@ -1179,8 +1175,8 @@ vec4_visitor::opt_register_coalesce() * in the register instead. */ if (to_mrf && scan_inst->mlen > 0) { - if (inst->dst.reg >= scan_inst->base_mrf && - inst->dst.reg < scan_inst->base_mrf + scan_inst->mlen) { + if (inst->dst.nr >= scan_inst->base_mrf && + inst->dst.nr < scan_inst->base_mrf + scan_inst->mlen) { break; } } else { @@ -1203,12 +1199,12 @@ vec4_visitor::opt_register_coalesce() vec4_instruction *scan_inst = _scan_inst; while (scan_inst != inst) { if (scan_inst->dst.file == GRF && - scan_inst->dst.reg == inst->src[0].reg && + scan_inst->dst.nr == inst->src[0].nr && scan_inst->dst.reg_offset == inst->src[0].reg_offset) { scan_inst->reswizzle(inst->dst.writemask, inst->src[0].swizzle); scan_inst->dst.file = inst->dst.file; - scan_inst->dst.reg = inst->dst.reg; + scan_inst->dst.nr = inst->dst.nr; scan_inst->dst.reg_offset = inst->dst.reg_offset; if (inst->saturate && inst->dst.type != scan_inst->dst.type) { @@ -1306,11 +1302,11 @@ vec4_visitor::split_virtual_grfs() */ foreach_block_and_inst(block, vec4_instruction, inst, cfg) { if (inst->dst.file == GRF && inst->regs_written > 1) - split_grf[inst->dst.reg] = false; + split_grf[inst->dst.nr] = false; for (int i = 0; i < 3; i++) { if (inst->src[i].file == GRF && inst->regs_read(i) > 1) - split_grf[inst->src[i].reg] = false; + split_grf[inst->src[i].nr] = false; } } @@ -1331,16 +1327,16 @@ vec4_visitor::split_virtual_grfs() } foreach_block_and_inst(block, vec4_instruction, inst, cfg) { - if (inst->dst.file == GRF && split_grf[inst->dst.reg] && + if (inst->dst.file == GRF && split_grf[inst->dst.nr] && inst->dst.reg_offset != 0) { - inst->dst.reg = (new_virtual_grf[inst->dst.reg] + + inst->dst.nr = (new_virtual_grf[inst->dst.nr] + inst->dst.reg_offset - 1); inst->dst.reg_offset = 0; } for (int i = 0; i < 3; i++) { - if (inst->src[i].file == GRF && split_grf[inst->src[i].reg] && + if (inst->src[i].file == GRF && split_grf[inst->src[i].nr] && inst->src[i].reg_offset != 0) { - inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] + + inst->src[i].nr = (new_virtual_grf[inst->src[i].nr] + inst->src[i].reg_offset - 1); inst->src[i].reg_offset = 0; } @@ -1383,10 +1379,10 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) switch (inst->dst.file) { case GRF: - fprintf(file, "vgrf%d.%d", inst->dst.reg, inst->dst.reg_offset); + fprintf(file, "vgrf%d.%d", inst->dst.nr, inst->dst.reg_offset); break; case MRF: - fprintf(file, "m%d", inst->dst.reg); + fprintf(file, "m%d", inst->dst.nr); break; case HW_REG: if (inst->dst.brw_reg::file == BRW_ARCHITECTURE_REGISTER_FILE) { @@ -1446,13 +1442,13 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) fprintf(file, "|"); switch (inst->src[i].file) { case GRF: - fprintf(file, "vgrf%d", inst->src[i].reg); + fprintf(file, "vgrf%d", inst->src[i].nr); break; case ATTR: - fprintf(file, "attr%d", inst->src[i].reg); + fprintf(file, "attr%d", inst->src[i].nr); break; case UNIFORM: - fprintf(file, "u%d", inst->src[i].reg); + fprintf(file, "u%d", inst->src[i].nr); break; case IMM: switch (inst->src[i].type) { @@ -1514,7 +1510,7 @@ vec4_visitor::dump_instruction(backend_instruction *be_inst, FILE *file) /* Don't print .0; and only VGRFs have reg_offsets and sizes */ if (inst->src[i].reg_offset != 0 && inst->src[i].file == GRF && - alloc.sizes[inst->src[i].reg] != 1) + alloc.sizes[inst->src[i].nr] != 1) fprintf(file, ".%d", inst->src[i].reg_offset); if (inst->src[i].file != IMM) { @@ -1572,7 +1568,7 @@ vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map, foreach_block_and_inst(block, vec4_instruction, inst, cfg) { /* We have to support ATTR as a destination for GL_FIXED fixup. */ if (inst->dst.file == ATTR) { - int grf = attribute_map[inst->dst.reg + inst->dst.reg_offset]; + int grf = attribute_map[inst->dst.nr + inst->dst.reg_offset]; /* All attributes used in the shader need to have been assigned a * hardware register by the caller @@ -1590,7 +1586,7 @@ vec4_visitor::lower_attributes_to_hw_regs(const int *attribute_map, if (inst->src[i].file != ATTR) continue; - int grf = attribute_map[inst->src[i].reg + inst->src[i].reg_offset]; + int grf = attribute_map[inst->src[i].nr + inst->src[i].reg_offset]; /* All attributes used in the shader need to have been assigned a * hardware register by the caller @@ -1790,7 +1786,7 @@ vec4_visitor::convert_to_hw_regs() struct brw_reg reg; switch (src.file) { case GRF: - reg = brw_vec8_grf(src.reg + src.reg_offset, 0); + reg = brw_vec8_grf(src.nr + src.reg_offset, 0); reg.type = src.type; reg.swizzle = src.swizzle; reg.abs = src.abs; @@ -1804,8 +1800,8 @@ vec4_visitor::convert_to_hw_regs() case UNIFORM: reg = stride(brw_vec4_grf(prog_data->base.dispatch_grf_start_reg + - (src.reg + src.reg_offset) / 2, - ((src.reg + src.reg_offset) % 2) * 4), + (src.nr + src.reg_offset) / 2, + ((src.nr + src.reg_offset) % 2) * 4), 0, 4, 1); reg.type = src.type; reg.swizzle = src.swizzle; @@ -1836,14 +1832,14 @@ vec4_visitor::convert_to_hw_regs() switch (inst->dst.file) { case GRF: - reg = brw_vec8_grf(dst.reg + dst.reg_offset, 0); + reg = brw_vec8_grf(dst.nr + dst.reg_offset, 0); reg.type = dst.type; reg.writemask = dst.writemask; break; case MRF: - assert(((dst.reg + dst.reg_offset) & ~(1 << 7)) < BRW_MAX_MRF(devinfo->gen)); - reg = brw_message_reg(dst.reg + dst.reg_offset); + assert(((dst.nr + dst.reg_offset) & ~(1 << 7)) < BRW_MAX_MRF(devinfo->gen)); + reg = brw_message_reg(dst.nr + dst.reg_offset); reg.type = dst.type; reg.writemask = dst.writemask; break; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp index 2be7b14..b986c12 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp @@ -271,7 +271,7 @@ try_copy_propagate(const struct brw_device_info *devinfo, for (int i = 1; i < 4; i++) { /* This is equals() except we don't care about the swizzle. */ if (value.file != entry->value[i]->file || - value.reg != entry->value[i]->reg || + value.nr != entry->value[i]->nr || value.reg_offset != entry->value[i]->reg_offset || value.type != entry->value[i]->type || value.negate != entry->value[i]->negate || @@ -431,7 +431,7 @@ vec4_visitor::opt_copy_propagation(bool do_constant_prop) if (inst->regs_read(i) != 1) continue; - int reg = (alloc.offsets[inst->src[i].reg] + + int reg = (alloc.offsets[inst->src[i].nr] + inst->src[i].reg_offset); /* Find the regs that each swizzle component came from. @@ -474,7 +474,7 @@ vec4_visitor::opt_copy_propagation(bool do_constant_prop) /* Track available source registers. */ if (inst->dst.file == GRF) { const int reg = - alloc.offsets[inst->dst.reg] + inst->dst.reg_offset; + alloc.offsets[inst->dst.nr] + inst->dst.reg_offset; /* Update our destination's current channel values. For a direct copy, * the value is the newly propagated source. Otherwise, we don't know diff --git a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp index 5a277f7..259f604 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_cse.cpp @@ -233,7 +233,7 @@ vec4_visitor::opt_cse_local(bblock_t *block) * overwrote. */ if (inst->dst.file == entry->generator->src[i].file && - inst->dst.reg == entry->generator->src[i].reg) { + inst->dst.nr == entry->generator->src[i].nr) { entry->remove(); ralloc_free(entry); break; diff --git a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h index e7929ec..4aa98d7 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h +++ b/src/mesa/drivers/dri/i965/brw_vec4_live_variables.h @@ -82,9 +82,9 @@ inline unsigned var_from_reg(const simple_allocator &alloc, const src_reg ®, unsigned c = 0) { - assert(reg.file == GRF && reg.reg < alloc.count && - reg.reg_offset < alloc.sizes[reg.reg] && c < 4); - return (4 * (alloc.offsets[reg.reg] + reg.reg_offset) + + assert(reg.file == GRF && reg.nr < alloc.count && + reg.reg_offset < alloc.sizes[reg.nr] && c < 4); + return (4 * (alloc.offsets[reg.nr] + reg.reg_offset) + BRW_GET_SWZ(reg.swizzle, c)); } @@ -92,9 +92,9 @@ inline unsigned var_from_reg(const simple_allocator &alloc, const dst_reg ®, unsigned c = 0) { - assert(reg.file == GRF && reg.reg < alloc.count && - reg.reg_offset < alloc.sizes[reg.reg] && c < 4); - return 4 * (alloc.offsets[reg.reg] + reg.reg_offset) + c; + assert(reg.file == GRF && reg.nr < alloc.count && + reg.reg_offset < alloc.sizes[reg.nr] && c < 4); + return 4 * (alloc.offsets[reg.nr] + reg.reg_offset) + c; } } /* namespace brw */ diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp index a49eca5..adad4e5 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp @@ -35,7 +35,7 @@ static void assign(unsigned int *reg_hw_locations, backend_reg *reg) { if (reg->file == GRF) { - reg->reg = reg_hw_locations[reg->reg] + reg->reg_offset; + reg->nr = reg_hw_locations[reg->nr] + reg->reg_offset; reg->reg_offset = 0; } } @@ -56,11 +56,11 @@ vec4_visitor::reg_allocate_trivial() foreach_block_and_inst(block, vec4_instruction, inst, cfg) { if (inst->dst.file == GRF) - virtual_grf_used[inst->dst.reg] = true; + virtual_grf_used[inst->dst.nr] = true; for (unsigned i = 0; i < 3; i++) { if (inst->src[i].file == GRF) - virtual_grf_used[inst->src[i].reg] = true; + virtual_grf_used[inst->src[i].nr] = true; } } @@ -297,7 +297,7 @@ can_use_scratch_for_source(const vec4_instruction *inst, unsigned i, /* See if any previous source in the same instructions reads scratch_reg */ for (unsigned n = 0; n < i; n++) { - if (inst->src[n].file == GRF && inst->src[n].reg == scratch_reg) + if (inst->src[n].file == GRF && inst->src[n].nr == scratch_reg) prev_inst_read_scratch_reg = true; } @@ -310,7 +310,7 @@ can_use_scratch_for_source(const vec4_instruction *inst, unsigned i, * it if the write is not conditional and the channels we write are * compatible with our read mask */ - if (prev_inst->dst.file == GRF && prev_inst->dst.reg == scratch_reg) { + if (prev_inst->dst.file == GRF && prev_inst->dst.nr == scratch_reg) { return (!prev_inst->predicate || prev_inst->opcode == BRW_OPCODE_SEL) && (brw_mask_for_swizzle(inst->src[i].swizzle) & ~prev_inst->dst.writemask) == 0; @@ -330,7 +330,7 @@ can_use_scratch_for_source(const vec4_instruction *inst, unsigned i, int n; for (n = 0; n < 3; n++) { if (prev_inst->src[n].file == GRF && - prev_inst->src[n].reg == scratch_reg) { + prev_inst->src[n].nr == scratch_reg) { prev_inst_read_scratch_reg = true; break; } @@ -379,18 +379,18 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill) * previous instruction, in which case we'll just reuse the scratch * reg for this instruction. */ - if (!can_use_scratch_for_source(inst, i, inst->src[i].reg)) { - spill_costs[inst->src[i].reg] += loop_scale; + if (!can_use_scratch_for_source(inst, i, inst->src[i].nr)) { + spill_costs[inst->src[i].nr] += loop_scale; if (inst->src[i].reladdr) - no_spill[inst->src[i].reg] = true; + no_spill[inst->src[i].nr] = true; } } } if (inst->dst.file == GRF) { - spill_costs[inst->dst.reg] += loop_scale; + spill_costs[inst->dst.nr] += loop_scale; if (inst->dst.reladdr) - no_spill[inst->dst.reg] = true; + no_spill[inst->dst.nr] = true; } switch (inst->opcode) { @@ -407,10 +407,10 @@ vec4_visitor::evaluate_spill_costs(float *spill_costs, bool *no_spill) case SHADER_OPCODE_GEN4_SCRATCH_WRITE: for (int i = 0; i < 3; i++) { if (inst->src[i].file == GRF) - no_spill[inst->src[i].reg] = true; + no_spill[inst->src[i].nr] = true; } if (inst->dst.file == GRF) - no_spill[inst->dst.reg] = true; + no_spill[inst->dst.nr] = true; break; default: @@ -445,7 +445,7 @@ vec4_visitor::spill_reg(int spill_reg_nr) int scratch_reg = -1; foreach_block_and_inst(block, vec4_instruction, inst, cfg) { for (unsigned int i = 0; i < 3; i++) { - if (inst->src[i].file == GRF && inst->src[i].reg == spill_reg_nr) { + if (inst->src[i].file == GRF && inst->src[i].nr == spill_reg_nr) { if (scratch_reg == -1 || !can_use_scratch_for_source(inst, i, scratch_reg)) { /* We need to unspill anyway so make sure we read the full vec4 @@ -455,19 +455,19 @@ vec4_visitor::spill_reg(int spill_reg_nr) */ scratch_reg = alloc.allocate(1); src_reg temp = inst->src[i]; - temp.reg = scratch_reg; + temp.nr = scratch_reg; temp.swizzle = BRW_SWIZZLE_XYZW; emit_scratch_read(block, inst, dst_reg(temp), inst->src[i], spill_offset); } assert(scratch_reg != -1); - inst->src[i].reg = scratch_reg; + inst->src[i].nr = scratch_reg; } } - if (inst->dst.file == GRF && inst->dst.reg == spill_reg_nr) { + if (inst->dst.file == GRF && inst->dst.nr == spill_reg_nr) { emit_scratch_write(block, inst, spill_offset); - scratch_reg = inst->dst.reg; + scratch_reg = inst->dst.nr; } } diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 7b11ac1..6038d90 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -633,7 +633,7 @@ src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type) init(); this->file = GRF; - this->reg = v->alloc.allocate(type_size_vec4(type)); + this->nr = v->alloc.allocate(type_size_vec4(type)); if (type->is_array() || type->is_record()) { this->swizzle = BRW_SWIZZLE_NOOP; @@ -651,7 +651,7 @@ src_reg::src_reg(class vec4_visitor *v, const struct glsl_type *type, int size) init(); this->file = GRF; - this->reg = v->alloc.allocate(type_size_vec4(type) * size); + this->nr = v->alloc.allocate(type_size_vec4(type) * size); this->swizzle = BRW_SWIZZLE_NOOP; @@ -663,7 +663,7 @@ dst_reg::dst_reg(class vec4_visitor *v, const struct glsl_type *type) init(); this->file = GRF; - this->reg = v->alloc.allocate(type_size_vec4(type)); + this->nr = v->alloc.allocate(type_size_vec4(type)); if (type->is_array() || type->is_record()) { this->writemask = WRITEMASK_XYZW; @@ -1615,7 +1615,7 @@ vec4_visitor::emit_scratch_write(bblock_t *block, vec4_instruction *inst, inst->insert_after(block, write); inst->dst.file = temp.file; - inst->dst.reg = temp.reg; + inst->dst.nr = temp.nr; inst->dst.reg_offset = temp.reg_offset; inst->dst.reladdr = NULL; } @@ -1642,10 +1642,10 @@ vec4_visitor::emit_resolve_reladdr(int scratch_loc[], bblock_t *block, *src.reladdr); /* Now handle scratch access on src */ - if (src.file == GRF && scratch_loc[src.reg] != -1) { + if (src.file == GRF && scratch_loc[src.nr] != -1) { dst_reg temp = dst_reg(this, glsl_type::vec4_type); - emit_scratch_read(block, inst, temp, src, scratch_loc[src.reg]); - src.reg = temp.reg; + emit_scratch_read(block, inst, temp, src, scratch_loc[src.nr]); + src.nr = temp.nr; src.reg_offset = temp.reg_offset; src.reladdr = NULL; } @@ -1671,17 +1671,17 @@ vec4_visitor::move_grf_array_access_to_scratch() */ foreach_block_and_inst(block, vec4_instruction, inst, cfg) { if (inst->dst.file == GRF && inst->dst.reladdr) { - if (scratch_loc[inst->dst.reg] == -1) { - scratch_loc[inst->dst.reg] = last_scratch; - last_scratch += this->alloc.sizes[inst->dst.reg]; + if (scratch_loc[inst->dst.nr] == -1) { + scratch_loc[inst->dst.nr] = last_scratch; + last_scratch += this->alloc.sizes[inst->dst.nr]; } for (src_reg *iter = inst->dst.reladdr; iter->reladdr; iter = iter->reladdr) { - if (iter->file == GRF && scratch_loc[iter->reg] == -1) { - scratch_loc[iter->reg] = last_scratch; - last_scratch += this->alloc.sizes[iter->reg]; + if (iter->file == GRF && scratch_loc[iter->nr] == -1) { + scratch_loc[iter->nr] = last_scratch; + last_scratch += this->alloc.sizes[iter->nr]; } } } @@ -1690,9 +1690,9 @@ vec4_visitor::move_grf_array_access_to_scratch() for (src_reg *iter = &inst->src[i]; iter->reladdr; iter = iter->reladdr) { - if (iter->file == GRF && scratch_loc[iter->reg] == -1) { - scratch_loc[iter->reg] = last_scratch; - last_scratch += this->alloc.sizes[iter->reg]; + if (iter->file == GRF && scratch_loc[iter->nr] == -1) { + scratch_loc[iter->nr] = last_scratch; + last_scratch += this->alloc.sizes[iter->nr]; } } } @@ -1718,8 +1718,8 @@ vec4_visitor::move_grf_array_access_to_scratch() /* Now that we have handled any (possibly recursive) reladdr scratch * accesses for dst we can safely do the scratch write for dst itself */ - if (inst->dst.file == GRF && scratch_loc[inst->dst.reg] != -1) - emit_scratch_write(block, inst, scratch_loc[inst->dst.reg]); + if (inst->dst.file == GRF && scratch_loc[inst->dst.nr] != -1) + emit_scratch_write(block, inst, scratch_loc[inst->dst.nr]); /* Now handle scratch access on any src. In this case, since inst->src[i] * already is a src_reg, we can just call emit_resolve_reladdr with @@ -1788,7 +1788,7 @@ vec4_visitor::move_uniform_array_access_to_pull_constants() if (inst->src[i].file != UNIFORM || !inst->src[i].reladdr) continue; - int uniform = inst->src[i].reg; + int uniform = inst->src[i].nr; if (inst->src[i].reladdr->reladdr) nested_reladdr = true; /* will need another pass */ @@ -1819,7 +1819,7 @@ vec4_visitor::move_uniform_array_access_to_pull_constants() pull_constant_loc[uniform]); inst->src[i].file = temp.file; - inst->src[i].reg = temp.reg; + inst->src[i].nr = temp.nr; inst->src[i].reg_offset = temp.reg_offset; inst->src[i].reladdr = NULL; } diff --git a/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp index e80b71b..a1f91d9 100644 --- a/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp +++ b/src/mesa/drivers/dri/i965/test_vec4_copy_propagation.cpp @@ -144,7 +144,7 @@ TEST_F(copy_propagation_test, test_swizzle_swizzle) copy_propagation(v); - EXPECT_EQ(test_mov->src[0].reg, a.reg); + EXPECT_EQ(test_mov->src[0].nr, a.nr); EXPECT_EQ(test_mov->src[0].swizzle, BRW_SWIZZLE4(SWIZZLE_Z, SWIZZLE_W, SWIZZLE_X, @@ -174,7 +174,7 @@ TEST_F(copy_propagation_test, test_swizzle_writemask) copy_propagation(v); /* should not copy propagate */ - EXPECT_EQ(test_mov->src[0].reg, b.reg); + EXPECT_EQ(test_mov->src[0].nr, b.nr); EXPECT_EQ(test_mov->src[0].swizzle, BRW_SWIZZLE4(SWIZZLE_W, SWIZZLE_W, SWIZZLE_W, diff --git a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp b/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp index 2f82461..d84e2e9 100644 --- a/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp +++ b/src/mesa/drivers/dri/i965/test_vec4_register_coalesce.cpp @@ -213,7 +213,7 @@ TEST_F(register_coalesce_test, test_dp4_grf) register_coalesce(v); - EXPECT_EQ(dp4->dst.reg, to.reg); + EXPECT_EQ(dp4->dst.nr, to.nr); EXPECT_EQ(dp4->dst.writemask, WRITEMASK_Y); } @@ -239,5 +239,5 @@ TEST_F(register_coalesce_test, test_channel_mul_grf) register_coalesce(v); - EXPECT_EQ(mul->dst.reg, to.reg); + EXPECT_EQ(mul->dst.nr, to.nr); } |