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| author | Kenneth Graunke <kenneth@whitecape.org> | 2014-02-25 12:21:40 -0800 |
|---|---|---|
| committer | Kenneth Graunke <kenneth@whitecape.org> | 2014-02-27 00:05:48 -0800 |
| commit | 9b1a6745f6b827170ac29a00510dbb740c81a116 (patch) | |
| tree | 704d460a60fa64dbbfb705130d8e358186bdbded /src | |
| parent | 51fc093421e4ed672ae3cba5a7f3695f3972e658 (diff) | |
| download | external_mesa3d-9b1a6745f6b827170ac29a00510dbb740c81a116.zip external_mesa3d-9b1a6745f6b827170ac29a00510dbb740c81a116.tar.gz external_mesa3d-9b1a6745f6b827170ac29a00510dbb740c81a116.tar.bz2 | |
i965: Only emit VS state pipe control workaround on IVB and BYT.
According to the BSpec's 3D workarounds page, this is unnecessary on
shipping Haswell hardware, and was never necessary on Broadwell. It
unfortunately doesn't say anything about Baytrail.
The workaround database confirms those results for Ivybridge, Haswell,
and Broadwell. Baytrail is less clear - one page says it's necessary,
while the other says it isn't. For now, be conservative and leave it
enabled.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_urb.c | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_vs_state.c | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 |
3 files changed, 5 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index 5273699..2653e9c 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -263,7 +263,8 @@ gen7_upload_urb(struct brw_context *brw) brw->urb.vs_start = push_constant_chunks; brw->urb.gs_start = push_constant_chunks + vs_chunks; - gen7_emit_vs_workaround_flush(brw); + if (brw->gen == 7 && !brw->is_haswell) + gen7_emit_vs_workaround_flush(brw); gen7_emit_urb_state(brw, brw->urb.nr_vs_entries, vs_size, brw->urb.vs_start, brw->urb.nr_gs_entries, gs_size, brw->urb.gs_start); diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c index 8381e1f..c4f1d26 100644 --- a/src/mesa/drivers/dri/i965/gen7_vs_state.c +++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c @@ -72,7 +72,8 @@ upload_vs_state(struct brw_context *brw) const int max_threads_shift = brw->is_haswell ? HSW_VS_MAX_THREADS_SHIFT : GEN6_VS_MAX_THREADS_SHIFT; - gen7_emit_vs_workaround_flush(brw); + if (!brw->is_haswell) + gen7_emit_vs_workaround_flush(brw); /* BRW_NEW_VS_BINDING_TABLE */ BEGIN_BATCH(2); diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index a06f298..98759e2 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -583,7 +583,7 @@ intel_emit_depth_stall_flushes(struct brw_context *brw) void gen7_emit_vs_workaround_flush(struct brw_context *brw) { - assert(brw->gen >= 7 && brw->gen <= 8); + assert(brw->gen == 7); brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE | PIPE_CONTROL_DEPTH_STALL, |